{"id":"https://openalex.org/W1991567807","doi":"https://doi.org/10.1109/fpl.2007.4380760","title":"Wirelength Prediction for FPGAs","display_name":"Wirelength Prediction for FPGAs","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W1991567807","doi":"https://doi.org/10.1109/fpl.2007.4380760","mag":"1991567807"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380760","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380760","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054424919","display_name":"Audip Pandit","orcid":null},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Audip Pandit","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","University of Arizona , Tucson#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]},{"raw_affiliation_string":"University of Arizona , Tucson#TAB#","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080974820","display_name":"Ali Akoglu","orcid":"https://orcid.org/0000-0001-7982-8991"},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ali Akoglu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","University of Arizona , Tucson#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]},{"raw_affiliation_string":"University of Arizona , Tucson#TAB#","institution_ids":["https://openalex.org/I138006243"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5054424919"],"corresponding_institution_ids":["https://openalex.org/I138006243"],"apc_list":null,"apc_paid":null,"fwci":0.7141,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.72102264,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"749","last_page":"752"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7437247633934021},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6379976272583008},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5441438555717468},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4448631703853607},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.39108455181121826},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3846270442008972}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7437247633934021},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6379976272583008},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5441438555717468},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4448631703853607},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.39108455181121826},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3846270442008972}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2007.4380760","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380760","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1568029617","https://openalex.org/W1970970490","https://openalex.org/W2001184806","https://openalex.org/W2015540924","https://openalex.org/W2095558812","https://openalex.org/W2101427886","https://openalex.org/W2109539905","https://openalex.org/W2111756578","https://openalex.org/W2135928627","https://openalex.org/W2139637699","https://openalex.org/W2140565566","https://openalex.org/W2143067779","https://openalex.org/W2148618168","https://openalex.org/W2162454075","https://openalex.org/W2162908425","https://openalex.org/W2169510384","https://openalex.org/W2218880787","https://openalex.org/W4255554251","https://openalex.org/W6650442278","https://openalex.org/W6683899246"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"FPGA":[0,95],"CAD":[1,38,96],"tools":[2],"require":[3],"wirelength":[4,48],"predictions":[5],"to":[6,31,45,54,70],"make":[7],"informed":[8],"decisions":[9],"through":[10],"clustering,":[11],"placement":[12,107],"and":[13,113],"routing":[14],"stages":[15],"towards":[16],"power,":[17],"area":[18],"or":[19],"delay":[20],"based":[21],"design":[22],"goals.":[23],"Unfortunately,":[24],"there":[25],"has":[26],"been":[27,68],"minimal":[28],"work":[29],"devoted":[30],"estimating":[32],"individual":[33,58],"wirelengths":[34],"early":[35],"in":[36,75,87,93],"the":[37,76,88,94,101],"flow.":[39,97],"Rent's":[40],"rule":[41],"can":[42],"be":[43,52],"used":[44,53],"generate":[46],"a":[47,84],"distribution":[49],"but":[50],"cannot":[51],"predict":[55],"lengths":[56],"of":[57,90,106,118],"wires.":[59],"Hence,":[60],"this":[61,82],"paper":[62],"explores":[63],"\"structural":[64],"metrics\"":[65],"that":[66,100],"have":[67],"found":[69],"possess":[71],"strong":[72],"predictive":[73],"qualities":[74],"ASIC":[77],"domain.":[78],"To":[79],"our":[80],"knowledge":[81],"is":[83],"first":[85],"study":[86],"application":[89],"these":[91],"metrics":[92,103],"Results":[98],"show":[99],"studied":[102],"capture":[104],"characteristics":[105],"optimization":[108],"carried":[109],"out":[110],"by":[111],"VPR,":[112],"hence,":[114],"are":[115],"good":[116],"indicators":[117],"post-placement":[119],"wirelengths.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}