{"id":"https://openalex.org/W1969243798","doi":"https://doi.org/10.1109/fpl.2007.4380735","title":"RIC Fast Adder and its Set-Tolerant Implementation in FPGAs","display_name":"RIC Fast Adder and its Set-Tolerant Implementation in FPGAs","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W1969243798","doi":"https://doi.org/10.1109/fpl.2007.4380735","mag":"1969243798"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380735","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380735","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021298843","display_name":"Eduardo Mesquita","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Eduardo Mesquita","raw_affiliation_strings":["Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","Fed. Univ. of Pelotas, Pelotas"],"affiliations":[{"raw_affiliation_string":"Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Fed. Univ. of Pelotas, Pelotas","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082071201","display_name":"Helen de Souza Franck","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Helen Franck","raw_affiliation_strings":["Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","Fed. Univ. of Pelotas, Pelotas"],"affiliations":[{"raw_affiliation_string":"Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Fed. Univ. of Pelotas, Pelotas","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070735330","display_name":"Luciano Agostini","orcid":"https://orcid.org/0000-0002-3421-5830"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luciano Agostini","raw_affiliation_strings":["Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","Fed. Univ. of Pelotas, Pelotas"],"affiliations":[{"raw_affiliation_string":"Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Fed. Univ. of Pelotas, Pelotas","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045089951","display_name":"Jos\u00e9 Lu\u00eds G\u00fcntzel","orcid":"https://orcid.org/0000-0002-7712-869X"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jose Luis Guntzel","raw_affiliation_strings":["Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","Fed. Univ. of Pelotas, Pelotas"],"affiliations":[{"raw_affiliation_string":"Informatics Department, Federal University of Pelotas-UFPel, Pelotas, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Fed. Univ. of Pelotas, Pelotas","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5021298843"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.05520653,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"638","last_page":"641"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9231064319610596},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8140112161636353},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7123234272003174},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4909246265888214},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4647623300552368},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4568023383617401},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4413042962551117},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43793195486068726},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4357760548591614},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4215741455554962},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4197211265563965},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3354324996471405},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33109018206596375},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.25599485635757446},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.25016462802886963},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1647677719593048},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09513905644416809},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.08856678009033203},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07926607131958008}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9231064319610596},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8140112161636353},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7123234272003174},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4909246265888214},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4647623300552368},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4568023383617401},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4413042962551117},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43793195486068726},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4357760548591614},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4215741455554962},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4197211265563965},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3354324996471405},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33109018206596375},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.25599485635757446},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.25016462802886963},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1647677719593048},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09513905644416809},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.08856678009033203},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07926607131958008},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2007.4380735","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380735","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1579847657","https://openalex.org/W2030501553","https://openalex.org/W2063272438","https://openalex.org/W2099569658","https://openalex.org/W2121395914","https://openalex.org/W2169213530","https://openalex.org/W3149410719"],"related_works":["https://openalex.org/W2197466303","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W1512285683","https://openalex.org/W2135636985","https://openalex.org/W2139569078","https://openalex.org/W2147419146","https://openalex.org/W1607849496","https://openalex.org/W2170504327","https://openalex.org/W2526300902"],"abstract_inverted_index":{"FPGA":[0,33],"is":[1,42],"currently":[2],"a":[3,68],"very":[4],"important":[5],"design":[6],"technology":[7,40],"to":[8,13,28,45,88],"implement":[9],"electronic":[10],"systems":[11],"due":[12],"its":[14,18,22],"high":[15,30],"logic":[16,31],"density,":[17],"fast":[19,70,91],"time-to-market":[20],"and":[21,78],"low":[23],"cost.":[24],"But":[25],"in":[26,60],"order":[27],"provide":[29],"density":[32],"devices":[34],"are":[35,55,58,97],"fabricated":[36],"with":[37],"nanometer":[38],"CMOS":[39],"that":[41,57],"becoming":[43],"susceptible":[44],"radiation-induced":[46],"soft":[47],"errors.":[48],"Among":[49],"these":[50],"errors,":[51],"single-event":[52],"transients":[53],"(SETs)":[54],"those":[56],"induced":[59],"the":[61,75],"user's":[62],"programmable":[63],"logic.":[64],"This":[65],"paper":[66],"presents":[67],"new":[69,82],"adder,":[71],"called":[72],"RIC":[73],"(Re-computing":[74],"Inverse":[76],"Carry-in)":[77],"shows":[79],"how":[80],"this":[81],"adder":[83],"architecture":[84],"may":[85],"be":[86],"used":[87],"build":[89],"SET-tolerant":[90],"adders.":[92],"Results":[93],"considering":[94],"FPGA-based":[95],"implementation":[96],"presented.":[98]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}