{"id":"https://openalex.org/W2043510289","doi":"https://doi.org/10.1109/fpl.2007.4380703","title":"A Tool for Exploring Hybrid FPGAs","display_name":"A Tool for Exploring Hybrid FPGAs","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2043510289","doi":"https://doi.org/10.1109/fpl.2007.4380703","mag":"2043510289"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380703","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102737997","display_name":"Chi Wai Yu","orcid":"https://orcid.org/0000-0002-3900-838X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Chi Wai Yu","raw_affiliation_strings":["Department of Computing, Imperial College London, London, UK","Imperial College London, #N#London"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, #N#London","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5102737997"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.8099,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.90191862,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"509","last_page":"510"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8945742249488831},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8007644414901733},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7725713849067688},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6233880519866943},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5380136370658875},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5065943002700806},{"id":"https://openalex.org/keywords/cover","display_name":"Cover (algebra)","score":0.487813264131546},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.47550636529922485},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.469779908657074},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4586517810821533},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4538695514202118},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34523245692253113},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10209497809410095},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.05663096904754639}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8945742249488831},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8007644414901733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7725713849067688},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6233880519866943},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5380136370658875},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5065943002700806},{"id":"https://openalex.org/C2780428219","wikidata":"https://www.wikidata.org/wiki/Q16952335","display_name":"Cover (algebra)","level":2,"score":0.487813264131546},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.47550636529922485},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.469779908657074},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4586517810821533},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4538695514202118},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34523245692253113},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10209497809410095},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.05663096904754639},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2007.4380703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380703","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6000000238418579,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1991973578","https://openalex.org/W2103883199","https://openalex.org/W2139637699","https://openalex.org/W2165055337","https://openalex.org/W6680692090"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1967938402","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450","https://openalex.org/W2386041993"],"abstract_inverted_index":{"We":[0],"show":[1],"that":[2],"the":[3,37,41,44,82,96],"VPH":[4,73,79],"tool":[5,35],"can":[6],"accurately":[7],"model":[8,22],"a":[9,13,27,48],"commercial":[10,58],"FPGA":[11,29,50],"on":[12],"set":[14],"of":[15,39,64,84],"benchmark":[16],"problems.":[17],"It":[18],"is":[19],"able":[20],"to":[21,54,74,80,94],"heterogeneous":[23],"embedded":[24],"blocks":[25],"in":[26,87],"hybrid":[28,65,85,97],"and":[30,43,60,68,90],"facilitates":[31],"design":[32,52],"exploration.":[33],"This":[34],"combines":[36],"benefits":[38],"both":[40],"VPR":[42,46],"VEB.":[45],"allows":[47],"larger":[49],"architecture":[51],"space":[53],"be":[55],"evaluated":[56],"than":[57],"tools,":[59],"VEB":[61],"enables":[62],"analysis":[63],"FPGAs.":[66],"Current":[67],"future":[69],"work":[70],"includes":[71],"extending":[72],"cover":[75],"other":[76],"devices,":[77],"using":[78],"explore":[81],"performance":[83],"FPGAs":[86,98],"various":[88],"architectures,":[89],"developing":[91],"automated":[92],"algorithms":[93],"optimize":[95],"for":[99],"domain":[100],"specific":[101],"applications.":[102]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}