{"id":"https://openalex.org/W2141497161","doi":"https://doi.org/10.1109/fpl.2007.4380675","title":"A Time-Triggered Network-on-Chip","display_name":"A Time-Triggered Network-on-Chip","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2141497161","doi":"https://doi.org/10.1109/fpl.2007.4380675","mag":"2141497161"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083205602","display_name":"Martin Schoeberl","orcid":"https://orcid.org/0000-0003-2366-382X"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Martin Schoeberl","raw_affiliation_strings":["Institute of Computer Engineering, University of Technology, Vienna, Austria","Vienna University of Technology, Vienna#TAB#"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of Technology, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Vienna University of Technology, Vienna#TAB#","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5083205602"],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":null,"apc_paid":null,"fwci":3.8505,"has_fulltext":false,"cited_by_count":50,"citation_normalized_percentile":{"value":0.93955755,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"377","last_page":"382"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.7330241203308105},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7266378402709961},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6980969309806824},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.6028813123703003},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6013720631599426},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5966126322746277},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5452956557273865},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5398908853530884},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.48720377683639526},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4513380825519562},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.42601537704467773},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3342362344264984},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.17910975217819214},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08770594000816345},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07876268029212952}],"concepts":[{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.7330241203308105},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7266378402709961},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6980969309806824},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.6028813123703003},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6013720631599426},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5966126322746277},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5452956557273865},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5398908853530884},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.48720377683639526},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4513380825519562},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.42601537704467773},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3342362344264984},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.17910975217819214},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08770594000816345},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07876268029212952},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2007.4380675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1498937403","https://openalex.org/W1555915743","https://openalex.org/W1606583766","https://openalex.org/W2059807497","https://openalex.org/W2079726719","https://openalex.org/W2089155985","https://openalex.org/W2107264649","https://openalex.org/W2107913358","https://openalex.org/W2109441937","https://openalex.org/W2115753002","https://openalex.org/W2119699246","https://openalex.org/W2157985422","https://openalex.org/W2159535674","https://openalex.org/W2171677863","https://openalex.org/W6636376874"],"related_works":["https://openalex.org/W1522111958","https://openalex.org/W2388672758","https://openalex.org/W2135981148","https://openalex.org/W2754086592","https://openalex.org/W4298431818","https://openalex.org/W2144357574","https://openalex.org/W2120080222","https://openalex.org/W2065289416","https://openalex.org/W3198758847","https://openalex.org/W4230458348"],"abstract_inverted_index":{"In":[0,42],"this":[1,43],"paper":[2,44],"we":[3,45],"propose":[4],"a":[5,21,33,39,48,64],"time-triggered":[6,50],"network-on-chip":[7],"(NoC)":[8],"for":[9,24,38,47,79,113],"on-chip":[10,89],"real-time":[11,26],"systems.":[12,27],"The":[13,67,82,97],"NoC":[14,31,51,112],"provides":[15],"time":[16],"predictable":[17],"on-and":[18],"off-chip":[19],"communication,":[20],"mandatory":[22],"feature":[23],"dependable":[25],"A":[28],"regular":[29],"structured":[30],"with":[32,87],"pseudo-static":[34],"communication":[35],"schedule":[36],"allows":[37],"high":[40],"bandwidth.":[41,56],"argue":[46],"simple,":[49],"structure":[52],"to":[53],"achieve":[54],"maximum":[55],"We":[57],"have":[58],"implemented":[59],"the":[60,74,94,101,104,110],"proposed":[61,111],"TT-NoC":[62],"in":[63,85],"low-cost":[65],"FPGA.":[66],"base":[68],"bandwidth":[69,76],"is":[70,84],"29":[71],"Gbit/s":[72,78],"and":[73,103],"peak":[75],"230":[77],"eight":[80],"nodes.":[81],"idea":[83],"line":[86],"current":[88],"multiprocessor":[90],"designs,":[91],"such":[92],"as":[93],"Cell":[95],"processor.":[96],"simple":[98],"design":[99],"of":[100,109],"network":[102,105],"interface":[106],"easies":[107],"certification":[108],"safety":[114],"critical":[115],"applications.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}