{"id":"https://openalex.org/W2155527235","doi":"https://doi.org/10.1109/fpl.2007.4380668","title":"A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs","display_name":"A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2155527235","doi":"https://doi.org/10.1109/fpl.2007.4380668","mag":"2155527235"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380668","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380668","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019600837","display_name":"Jens Hagemeyer","orcid":"https://orcid.org/0009-0005-9943-8081"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jens Hagemeyer","raw_affiliation_strings":["System and Circuit Technology, University of Paderborn, Germany"],"affiliations":[{"raw_affiliation_string":"System and Circuit Technology, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019897299","display_name":"Boris Kettelhoit","orcid":null},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Boris Kettelhoit","raw_affiliation_strings":["System and Circuit Technology, University of Paderborn, Germany"],"affiliations":[{"raw_affiliation_string":"System and Circuit Technology, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041162707","display_name":"Markus Koester","orcid":null},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Koester","raw_affiliation_strings":["System and Circuit Technology, University of Paderborn, Germany"],"affiliations":[{"raw_affiliation_string":"System and Circuit Technology, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028498307","display_name":"Mario Porrmann","orcid":"https://orcid.org/0000-0003-1005-5753"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mario Porrmann","raw_affiliation_strings":["System and Circuit Technology, University of Paderborn, Germany"],"affiliations":[{"raw_affiliation_string":"System and Circuit Technology, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5019600837"],"corresponding_institution_ids":["https://openalex.org/I206945453"],"apc_list":null,"apc_paid":null,"fwci":4.1297,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.93950688,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"2147","issue":null,"first_page":"331","last_page":"338"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8363367915153503},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.752398669719696},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7074599266052246},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6916598677635193},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.6447945237159729},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6094376444816589},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5826074481010437},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5268760323524475},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.5248432159423828},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.511583149433136},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.4301976263523102},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4259773790836334},{"id":"https://openalex.org/keywords/communications-system","display_name":"Communications system","score":0.41823646426200867},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1259593963623047},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11049461364746094},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0935860276222229}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8363367915153503},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.752398669719696},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7074599266052246},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6916598677635193},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.6447945237159729},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6094376444816589},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5826074481010437},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5268760323524475},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.5248432159423828},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.511583149433136},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.4301976263523102},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4259773790836334},{"id":"https://openalex.org/C101765175","wikidata":"https://www.wikidata.org/wiki/Q577764","display_name":"Communications system","level":2,"score":0.41823646426200867},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1259593963623047},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11049461364746094},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0935860276222229},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2007.4380668","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380668","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:pub.librecat.org:2472743","is_oa":false,"landing_page_url":"https://pub.uni-bielefeld.de/record/2472743","pdf_url":null,"source":{"id":"https://openalex.org/S4306401671","display_name":"PUB \u2013 Publications at Bielefeld University (Bielefeld University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I20121455","host_organization_name":"Bielefeld University","host_organization_lineage":["https://openalex.org/I20121455"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. In:  <em>Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)</em>. Amsterdam, Netherlands;  2007: 331-338.","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1483813241","https://openalex.org/W1506053183","https://openalex.org/W1553483971","https://openalex.org/W1576594927","https://openalex.org/W1969643475","https://openalex.org/W2000688841","https://openalex.org/W2104371908","https://openalex.org/W2106767353","https://openalex.org/W2130193491","https://openalex.org/W2149052212","https://openalex.org/W2149935414","https://openalex.org/W2152373011","https://openalex.org/W2165666359","https://openalex.org/W3140858214","https://openalex.org/W6629044667","https://openalex.org/W6633208539","https://openalex.org/W6684387282"],"related_works":["https://openalex.org/W4245901115","https://openalex.org/W3036411830","https://openalex.org/W1521892965","https://openalex.org/W2130193491","https://openalex.org/W2058520863","https://openalex.org/W1519183141","https://openalex.org/W3151101169","https://openalex.org/W1659609664","https://openalex.org/W2142315955","https://openalex.org/W2296115084"],"abstract_inverted_index":{"The":[0,43],"ability":[1],"of":[2,5,11,21,28,55,73,94,113],"partial":[3],"reconfiguration":[4],"today's":[6],"FPGAs":[7],"allows":[8],"the":[9,19,26,59,62,67,71,84,92,107,130],"exchange":[10],"dynamic":[12,63,85],"system":[13,32,49,64,86],"components":[14,87],"at":[15,89],"run-time,":[16],"which":[17,79,105],"enables":[18],"realization":[20],"self-reconfigurable":[22],"systems.":[23],"To":[24],"ease":[25],"design":[27,38,44,68,93],"a":[29,74,100,118,124,136],"partially":[30],"reconfigurable":[31,41],"this":[33],"paper":[34],"presents":[35],"an":[36,96,116],"integrated":[37],"flow":[39,45,69],"for":[40,48,58],"architectures.":[42],"includes":[46],"tools":[47],"partitioning,":[50],"floorplanning,":[51],"and":[52,61,135,141],"automatic":[53],"generation":[54],"configuration":[56],"data":[57],"static":[60],"components.":[65],"Furthermore,":[66],"comprises":[70],"implementation":[72,138],"homogeneous":[75],"on-chip":[76,97],"communication":[77,98,108,119],"infrastructure,":[78],"is":[80,103,121],"used":[81],"to":[82,145],"interconnect":[83],"placed":[88],"run-time.":[90],"For":[91],"such":[95],"infrastructure":[99,120],"layer":[101],"model":[102],"introduced,":[104],"divides":[106],"into":[109],"five":[110],"different":[111],"layers":[112],"abstraction.":[114],"As":[115],"example":[117],"realized":[122],"on":[123,129],"Xilinx":[125],"Virtex-2":[126],"FPGA":[127],"based":[128],"Wishbone":[131],"protocol.":[132],"A":[133],"tristate-based":[134],"slice-based":[137],"are":[139],"presented":[140],"analyzed":[142],"with":[143],"respect":[144],"efficiency.":[146]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":8}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}