{"id":"https://openalex.org/W2157727391","doi":"https://doi.org/10.1109/fpl.2007.4380666","title":"Time Predictable CPU and DMA Shared Memory Access","display_name":"Time Predictable CPU and DMA Shared Memory Access","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2157727391","doi":"https://doi.org/10.1109/fpl.2007.4380666","mag":"2157727391"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000020181","display_name":"Christof Pitter","orcid":null},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Christof Pitter","raw_affiliation_strings":["Institute of Computer Engineering, University of Technology, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of Technology, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083205602","display_name":"Martin Schoeberl","orcid":"https://orcid.org/0000-0003-2366-382X"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Martin Schoeberl","raw_affiliation_strings":["Institute of Computer Engineering, University of Technology, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of Technology, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5000020181"],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":null,"apc_paid":null,"fwci":2.2237,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.88474771,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"317","last_page":"322"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8917253017425537},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6680373549461365},{"id":"https://openalex.org/keywords/embedded-java","display_name":"Embedded Java","score":0.5384352803230286},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.48332926630973816},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4561237394809723},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.40877753496170044},{"id":"https://openalex.org/keywords/java","display_name":"Java","score":0.39339548349380493},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3543078303337097},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32985448837280273},{"id":"https://openalex.org/keywords/java-concurrency","display_name":"Java concurrency","score":0.13797321915626526},{"id":"https://openalex.org/keywords/real-time-java","display_name":"Real time Java","score":0.12817612290382385},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.1051797866821289}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8917253017425537},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6680373549461365},{"id":"https://openalex.org/C175224512","wikidata":"https://www.wikidata.org/wiki/Q1334980","display_name":"Embedded Java","level":5,"score":0.5384352803230286},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.48332926630973816},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4561237394809723},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.40877753496170044},{"id":"https://openalex.org/C548217200","wikidata":"https://www.wikidata.org/wiki/Q251","display_name":"Java","level":2,"score":0.39339548349380493},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3543078303337097},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32985448837280273},{"id":"https://openalex.org/C181907185","wikidata":"https://www.wikidata.org/wiki/Q1100098","display_name":"Java concurrency","level":4,"score":0.13797321915626526},{"id":"https://openalex.org/C132106392","wikidata":"https://www.wikidata.org/wiki/Q1373903","display_name":"Real time Java","level":3,"score":0.12817612290382385},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.1051797866821289}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/fpl.2007.4380666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.562.9518","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.562.9518","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ti.tuwien.ac.at/cps/people/pitter/publications/jopvga_fpl2007.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.69.5079","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.69.5079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ti.tuwien.ac.at/rts/people/schoeberl/publications/jopvga_fpl2007.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1524254874","https://openalex.org/W1563826489","https://openalex.org/W1606583766","https://openalex.org/W2032742044","https://openalex.org/W2086061827","https://openalex.org/W2089757303","https://openalex.org/W2097465082","https://openalex.org/W2100399943","https://openalex.org/W2106974838","https://openalex.org/W2262960161","https://openalex.org/W3023392404","https://openalex.org/W4285719527","https://openalex.org/W6776953718"],"related_works":["https://openalex.org/W1780290295","https://openalex.org/W2121819567","https://openalex.org/W2098862077","https://openalex.org/W2145152293","https://openalex.org/W1553103764","https://openalex.org/W2167995300","https://openalex.org/W2381806172","https://openalex.org/W2142696759","https://openalex.org/W2756307308","https://openalex.org/W2070452068"],"abstract_inverted_index":{"In":[0,69],"this":[1,70],"paper,":[2,71],"we":[3,72],"propose":[4],"a":[5,9,58,74,80,87],"first":[6],"step":[7],"towards":[8],"time":[10,39,75],"predictable":[11,76],"computer":[12],"architecture":[13],"for":[14,32,53],"single-chip":[15],"multiprocessing":[16],"(CMP).":[17],"CMP":[18,28],"is":[19,29,119],"the":[20,48,67,111,120,125,130],"actual":[21],"trend":[22],"in":[23,114,138],"server":[24],"and":[25,79,95,105,128],"desktop":[26],"systems.":[27],"even":[30],"considered":[31],"embedded":[33],"realtime":[34],"systems,":[35],"where":[36],"worst-case":[37],"execution":[38],"(WCET)":[40],"estimates":[41],"are":[42],"of":[43,50],"primary":[44],"importance.":[45],"We":[46,93,108],"attack":[47],"problem":[49],"WCET":[51,106],"analysis":[52,104],"several":[54],"processing":[55],"units":[56],"accesing":[57],"shared":[59],"resource":[60],"(the":[61],"main":[62],"memory)":[63],"by":[64,132],"support":[65],"from":[66],"hardware.":[68,140],"combine":[73],"Java":[77],"processor":[78],"direct":[81],"memory":[82],"access":[83,89],"(DMA)":[84],"unit":[85],"with":[86,100,135],"regular":[88],"pattern":[90],"(VGA":[91],"controller).":[92],"analyze":[94],"evaluate":[96,129],"different":[97,126],"arbitration":[98],"schemes":[99],"respect":[101],"to":[102,123],"schedulability":[103],"analysis.":[107],"also":[109],"implement":[110],"various":[112],"combinations":[113],"an":[115],"FPGA.":[116],"An":[117],"FPGA":[118],"ideal":[121],"platform":[122],"verify":[124],"concepts":[127],"results":[131],"running":[133],"applications":[134],"industrial":[136],"background":[137],"real":[139]},"counts_by_year":[{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}