{"id":"https://openalex.org/W2002826637","doi":"https://doi.org/10.1109/fpl.2007.4380653","title":"On the Feasibility of Early Routing Capacitance Estimation for FPGAs","display_name":"On the Feasibility of Early Routing Capacitance Estimation for FPGAs","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2002826637","doi":"https://doi.org/10.1109/fpl.2007.4380653","mag":"2002826637"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380653","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380653","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071550327","display_name":"Jonathan Clarke","orcid":"https://orcid.org/0000-0003-1495-7746"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Jonathan A. Clarke","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Imperial College London, #N#London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, #N#London","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George A. Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Imperial College London, #N#London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, #N#London","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Imperial College London, #N#London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, #N#London","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5071550327"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.7176,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72524138,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"234","last_page":"239"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.8285014629364014},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.8037703037261963},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6667612791061401},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.61981201171875},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.49042341113090515},{"id":"https://openalex.org/keywords/parasitic-capacitance","display_name":"Parasitic capacitance","score":0.44949811697006226},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.447859525680542},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.44043847918510437},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39661717414855957},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.38837921619415283},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2923780083656311},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2543798089027405},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1914680302143097}],"concepts":[{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.8285014629364014},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.8037703037261963},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6667612791061401},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.61981201171875},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.49042341113090515},{"id":"https://openalex.org/C154318817","wikidata":"https://www.wikidata.org/wiki/Q2157249","display_name":"Parasitic capacitance","level":4,"score":0.44949811697006226},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.447859525680542},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.44043847918510437},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39661717414855957},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.38837921619415283},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2923780083656311},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2543798089027405},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1914680302143097},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2007.4380653","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380653","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.385.6524","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.6524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cas.ee.ic.ac.uk/people/gac1/pubs/JonFPL07.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G6672801631","display_name":null,"funder_award_id":"EP/E00024X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2097798204","https://openalex.org/W2100903835","https://openalex.org/W2106655287","https://openalex.org/W2118014020","https://openalex.org/W2122628351","https://openalex.org/W2133500791","https://openalex.org/W2146589686","https://openalex.org/W2159022270","https://openalex.org/W2170510975","https://openalex.org/W2504355181","https://openalex.org/W3149866969"],"related_works":["https://openalex.org/W3183044703","https://openalex.org/W2082487009","https://openalex.org/W2156550631","https://openalex.org/W2132668926","https://openalex.org/W2042759115","https://openalex.org/W1973505932","https://openalex.org/W2547355295","https://openalex.org/W2914442136","https://openalex.org/W2098851424","https://openalex.org/W2159053194"],"abstract_inverted_index":{"Knowing":[0],"the":[1,14,35,48,77,89,92,96],"capacitance":[2,36,53,78],"of":[3,37,50,79,95],"circuit":[4,24],"nets":[5,80],"in":[6],"an":[7],"FPGA":[8],"design":[9],"is":[10,25,29],"essential":[11],"when":[12],"computing":[13],"dynamic":[15],"power":[16,59],"consumed":[17],"by":[18],"switching":[19],"these":[20],"nets.":[21],"Before":[22],"a":[23,72],"placed,":[26],"however,":[27],"there":[28],"little":[30],"information":[31],"available":[32],"to":[33,40,56,63,66],"allow":[34,57],"routing":[38,52,68],"wires":[39],"be":[41,64],"estimated.":[42],"In":[43],"this":[44,86],"paper":[45],"we":[46],"study":[47],"feasibility":[49],"estimating":[51,76],"before":[54,81],"RTL-synthesis":[55,82],"high-level":[58],"consumption":[60],"optimization":[61],"algorithms":[62],"able":[65],"target":[67],"power.":[69],"We":[70],"propose":[71],"novel":[73],"method":[74,87],"for":[75],"and":[83,91],"show":[84],"that":[85],"improves":[88],"accuracy":[90],"rank":[93],"ordering":[94],"net-by-net":[97],"estimates":[98],"made":[99],"over":[100],"existing":[101],"fan-out":[102],"based":[103],"techniques.":[104]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
