{"id":"https://openalex.org/W2111683449","doi":"https://doi.org/10.1109/fpl.2007.4380649","title":"Improving Pipelined Soft Processors with Multithreading","display_name":"Improving Pipelined Soft Processors with Multithreading","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2111683449","doi":"https://doi.org/10.1109/fpl.2007.4380649","mag":"2111683449"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380649","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380649","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025833637","display_name":"Martin Labrecque","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Martin Labrecque","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Canada","Toronto Univ., Toronto"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Toronto Univ., Toronto","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110755517","display_name":"J. Gregory Steffan","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Gregory Steffan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Canada","Toronto Univ., Toronto"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Toronto Univ., Toronto","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025833637"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":3.4944,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.92526758,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"210","last_page":"215"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.8663758039474487},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8067269921302795},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6110289096832275},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5895324349403381},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5059420466423035},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.46519386768341064},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4357561469078064},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.4279109537601471},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.420623779296875},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.15910330414772034},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1295628845691681}],"concepts":[{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.8663758039474487},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8067269921302795},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6110289096832275},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5895324349403381},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5059420466423035},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.46519386768341064},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4357561469078064},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.4279109537601471},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.420623779296875},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.15910330414772034},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1295628845691681},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/fpl.2007.4380649","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380649","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.66.1203","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.66.1203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.utoronto.ca/~martinl/papers/fpl07.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.68.4762","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.68.4762","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.utoronto.ca/~martinl/papers/fpl07.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.75.3619","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.75.3619","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~steffan/papers/fpl07.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W163837928","https://openalex.org/W1603717301","https://openalex.org/W1686420892","https://openalex.org/W2068419076","https://openalex.org/W2072076019","https://openalex.org/W2121076909","https://openalex.org/W2128748139","https://openalex.org/W2157855196","https://openalex.org/W2157904683","https://openalex.org/W6606669339","https://openalex.org/W6636251665","https://openalex.org/W6668426652"],"related_works":["https://openalex.org/W2118532220","https://openalex.org/W4240807263","https://openalex.org/W2913446311","https://openalex.org/W1532726325","https://openalex.org/W2115561485","https://openalex.org/W2354938433","https://openalex.org/W3142147837","https://openalex.org/W1987511199","https://openalex.org/W4231178640","https://openalex.org/W2107241550"],"abstract_inverted_index":{"Designers":[0],"of":[1,17,26,31,79,82,88],"FPGA-based":[2],"systems":[3],"are":[4,65],"increasingly":[5],"including":[6],"soft":[7,33,63],"processors-processors":[8],"implemented":[9],"in":[10,28],"programmable":[11],"logic-in":[12],"their":[13,74],"designs.":[14,50],"Any":[15],"combination":[16],"area,":[18],"clock":[19],"frequency,":[20],"performance,":[21],"and":[22,59,68,86],"power":[23],"may":[24],"be":[25],"importance":[27],"the":[29,42,77,83],"choice":[30],"a":[32],"processor":[34],"design":[35],"to":[36,47],"use,":[37],"motivating":[38],"area":[39,71],"efficiency":[40],"as":[41],"best":[43],"metric":[44],"with":[45],"which":[46],"compare":[48],"potential":[49],"In":[51],"this":[52],"paper":[53],"we":[54],"demonstrate":[55],"that":[56],"3,":[57],"5,":[58],"7-stage":[60],"pipelined":[61],"multithreaded":[62],"processors":[64],"33%,":[66],"77%,":[67],"106%":[69],"more":[70],"efficient":[72],"than":[73],"single-threade":[75],"counterparts,":[76],"result":[78],"careful":[80],"tuning":[81],"architecture,":[84],"ISA,":[85],"number":[87],"threads.":[89]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
