{"id":"https://openalex.org/W2154013582","doi":"https://doi.org/10.1109/fpl.2007.4380648","title":"Embedded Programmable Logic Core Enhancements for System Bus Interfaces","display_name":"Embedded Programmable Logic Core Enhancements for System Bus Interfaces","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2154013582","doi":"https://doi.org/10.1109/fpl.2007.4380648","mag":"2154013582"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380648","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110246862","display_name":"B.R. Quinton","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Bradley R. Quinton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J.E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5110246862"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.3183,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65811884,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"202","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.704825222492218},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.691927433013916},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6436464786529541},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6346454620361328},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6279888153076172},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6132519245147705},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.5098368525505066},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4842357337474823},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4714401960372925},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46836745738983154},{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.43124639987945557},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4270564913749695},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4151723086833954},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35244160890579224},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20725122094154358},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.14557379484176636},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12209710478782654},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06854668259620667}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.704825222492218},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.691927433013916},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6436464786529541},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6346454620361328},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6279888153076172},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6132519245147705},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.5098368525505066},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4842357337474823},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4714401960372925},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46836745738983154},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.43124639987945557},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4270564913749695},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4151723086833954},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35244160890579224},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20725122094154358},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.14557379484176636},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12209710478782654},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06854668259620667},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2007.4380648","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.215.1075","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.215.1075","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/~stevew/papers/pdf/fpl07a.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5400000214576721,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1901233933","https://openalex.org/W2035626076","https://openalex.org/W2077892593","https://openalex.org/W2100580949","https://openalex.org/W2104603273","https://openalex.org/W2116007187","https://openalex.org/W2121903852","https://openalex.org/W2129547250","https://openalex.org/W2147419146","https://openalex.org/W2155372376","https://openalex.org/W2162546785","https://openalex.org/W4246961877","https://openalex.org/W6683964721"],"related_works":["https://openalex.org/W1904803855","https://openalex.org/W3013792460","https://openalex.org/W2376859467","https://openalex.org/W4389045693","https://openalex.org/W2990957507","https://openalex.org/W2374125170","https://openalex.org/W2360552902","https://openalex.org/W2584013459","https://openalex.org/W1839326631","https://openalex.org/W2047993371"],"abstract_inverted_index":{"Programmable":[0],"logic":[1,27],"cores":[2],"(PLCs)":[3],"offer":[4],"a":[5,12,18,51],"means":[6],"of":[7,39,48,83],"providing":[8],"post-fabrication":[9],"re-configurability":[10],"to":[11,81,87],"SoC":[13,50,67],"design.":[14],"Circuits":[15],"implemented":[16,63],"in":[17,64],"PLC":[19,44,85],"will":[20],"inevitably":[21],"have":[22],"lower":[23],"timing":[24,105],"performance":[25],"and":[26,45,66,77,113],"density":[28],"than":[29,133],"fixed":[30],"function":[31],"circuits.":[32],"This":[33],"fundamental":[34],"mismatch":[35],"makes":[36],"the":[37,40,43,46,49,84,128],"design":[38],"interface":[41,104],"between":[42,61],"rest":[47],"challenging":[52],"problem.":[53],"In":[54],"this":[55,100],"paper":[56],"we":[57],"focus":[58],"on":[59,98],"interfaces":[60],"circuits":[62,119,136],"PLCs":[65],"system":[68,91,122],"busses.":[69],"We":[70,125],"demonstrate":[71],"problems":[72],"with":[73],"existing":[74],"implementation":[75],"options":[76],"then":[78],"propose":[79],"modifications":[80],"parts":[82],"architecture":[86,102],"enable":[88],"more":[89],"efficient":[90],"bus":[92,123,141],"interfaces.":[93,124,142],"Our":[94],"results":[95],"show":[96,126],"that,":[97],"average,":[99],"modified":[101],"improves":[103,114],"by":[106,111,116],"36.4%,":[107],"reduces":[108],"CLB":[109],"usage":[110],"7.9%":[112],"routability":[115],"28.8%":[117],"for":[118,135],"that":[120,127,137],"require":[121,140],"area":[129],"overhead":[130],"is":[131],"less":[132],"0.5%":[134],"do":[138],"not":[139]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}