{"id":"https://openalex.org/W2115207949","doi":"https://doi.org/10.1109/fpl.2007.4380644","title":"A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects","display_name":"A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2115207949","doi":"https://doi.org/10.1109/fpl.2007.4380644","mag":"2115207949"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380644","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380644","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012238748","display_name":"Graham Schelle","orcid":null},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Graham Schelle","raw_affiliation_strings":["Dept. of Computer Science, University of Colorado at Boulder, Boulder, CO, USA","University of Colorado \u2010 Boulder"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science, University of Colorado at Boulder, Boulder, CO, USA","institution_ids":["https://openalex.org/I188538660"]},{"raw_affiliation_string":"University of Colorado \u2010 Boulder","institution_ids":["https://openalex.org/I188538660"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083632297","display_name":"Jeff Fifield","orcid":null},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeff Fifield","raw_affiliation_strings":["Dept. of Computer Science, University of Colorado at Boulder, Boulder, CO, USA","University of Colorado \u2010 Boulder"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science, University of Colorado at Boulder, Boulder, CO, USA","institution_ids":["https://openalex.org/I188538660"]},{"raw_affiliation_string":"University of Colorado \u2010 Boulder","institution_ids":["https://openalex.org/I188538660"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059685104","display_name":"Dirk Grunwald","orcid":"https://orcid.org/0000-0002-3174-0904"},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dirk Grunwald","raw_affiliation_strings":["Dept. of Computer Science, University of Colorado at Boulder, Boulder, CO, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science, University of Colorado at Boulder, Boulder, CO, USA","institution_ids":["https://openalex.org/I188538660"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I188538660"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"177","last_page":"182"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9865000247955322,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8216392993927002},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7401070594787598},{"id":"https://openalex.org/keywords/software-defined-radio","display_name":"Software-defined radio","score":0.729508638381958},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6655466556549072},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.641562283039093},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6339924335479736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6275266408920288},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6060609221458435},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5546954274177551},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5368108749389648},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20436328649520874},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14208009839057922},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08947712182998657}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8216392993927002},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7401070594787598},{"id":"https://openalex.org/C171115542","wikidata":"https://www.wikidata.org/wiki/Q1331892","display_name":"Software-defined radio","level":2,"score":0.729508638381958},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6655466556549072},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.641562283039093},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6339924335479736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6275266408920288},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6060609221458435},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5546954274177551},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5368108749389648},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20436328649520874},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14208009839057922},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08947712182998657},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2007.4380644","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380644","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1499458427","https://openalex.org/W1541235314","https://openalex.org/W1561157983","https://openalex.org/W2104601950","https://openalex.org/W2117099910","https://openalex.org/W2123184444","https://openalex.org/W2123624675","https://openalex.org/W2172212694","https://openalex.org/W4285719527","https://openalex.org/W6633748229","https://openalex.org/W6675862387"],"related_works":["https://openalex.org/W2355663289","https://openalex.org/W2106913410","https://openalex.org/W4380372336","https://openalex.org/W2354248671","https://openalex.org/W2359134391","https://openalex.org/W2594116857","https://openalex.org/W2947628004","https://openalex.org/W2935229758","https://openalex.org/W2352791832","https://openalex.org/W2387385112"],"abstract_inverted_index":{"Network":[0,40],"on":[1,41],"Chips":[2],"are":[3,24,37,117],"becoming":[4],"a":[5,25,79,83,91,97,103],"common":[6],"onchip":[7],"interconnect":[8],"for":[9],"both":[10],"FPGA":[11],"and":[12,55,76,99,113,126],"mainstream":[13],"processor":[14],"designs.":[15],"At":[16],"the":[17,44,52,58,71,121],"same":[18],"time,":[19],"software":[20],"defined":[21],"radios":[22],"(SDR)":[23],"new":[26],"application":[27,125],"field":[28],"that":[29,64],"is":[30],"gaining":[31],"much":[32],"attention.":[33],"As":[34],"SDR":[35,80],"tasks":[36],"mapped":[38],"onto":[39,82],"Chip":[42],"architectures,":[43],"typically":[45],"streaming":[46],"nature":[47],"of":[48,60,73,78,123],"samples":[49],"will":[50],"stress":[51],"NoC":[53,84,98,114],"itself":[54],"possibly":[56],"hurt":[57],"performance":[59],"other":[61],"applications":[62],"using":[63,86],"NoC.":[65],"In":[66],"this":[67,124],"paper,":[68],"we":[69],"present":[70],"results":[72],"our":[74],"partitioning":[75],"placement":[77,108],"transmitter":[81,93],"architecture":[85,111,127],"an":[87],"FPGA.":[88],"We":[89],"use":[90],"802.11a":[92],"example":[94],"partitioned":[95],"across":[96],"compare":[100],"it":[101],"to":[102,119],"handcrafted":[104],"design.":[105],"Additionally,":[106],"various":[107],"schemes,":[109],"runtime":[110],"loads":[112],"access":[115],"methods":[116],"examined":[118],"determine":[120],"feasibility":[122],"combination.":[128]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}