{"id":"https://openalex.org/W2151614223","doi":"https://doi.org/10.1109/fpl.2007.4380635","title":"Improving Timing-Driven FPGA Packing with Physical Information","display_name":"Improving Timing-Driven FPGA Packing with Physical Information","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2151614223","doi":"https://doi.org/10.1109/fpl.2007.4380635","mag":"2151614223"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2007.4380635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009053605","display_name":"Doris T. Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Doris T. Chen","raw_affiliation_strings":["University of Waterloo, Waterloo, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005615652","display_name":"Kristofer Vorwerk","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kristofer Vorwerk","raw_affiliation_strings":["University of Waterloo, Waterloo, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007026340","display_name":"Andrew Kennings","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andrew Kennings","raw_affiliation_strings":["University of Waterloo, Waterloo, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009053605"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":2.4587,"has_fulltext":false,"cited_by_count":46,"citation_normalized_percentile":{"value":0.89506269,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"117","last_page":"123"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8346793055534363},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7749366760253906},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.5998592376708984},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5493228435516357},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4641939401626587},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4578165113925934},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4241173267364502},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3887888789176941},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3807412087917328},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.32563531398773193},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.16513320803642273},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11035004258155823},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09846580028533936},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.07303553819656372}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8346793055534363},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7749366760253906},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.5998592376708984},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5493228435516357},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4641939401626587},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4578165113925934},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4241173267364502},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3887888789176941},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3807412087917328},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.32563531398773193},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.16513320803642273},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11035004258155823},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09846580028533936},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.07303553819656372},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2007.4380635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2007.4380635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1522095270","https://openalex.org/W1523051745","https://openalex.org/W1575153928","https://openalex.org/W1583136220","https://openalex.org/W1989931041","https://openalex.org/W2002641171","https://openalex.org/W2004015744","https://openalex.org/W2029459574","https://openalex.org/W2029541370","https://openalex.org/W2106448546","https://openalex.org/W2109769138","https://openalex.org/W2113267287","https://openalex.org/W2121244114","https://openalex.org/W2139637699","https://openalex.org/W2150281391","https://openalex.org/W4238070904","https://openalex.org/W4241806018","https://openalex.org/W6635135688","https://openalex.org/W6676095809","https://openalex.org/W6678158601"],"related_works":["https://openalex.org/W3183044703","https://openalex.org/W2132668926","https://openalex.org/W2082487009","https://openalex.org/W2156550631","https://openalex.org/W2042759115","https://openalex.org/W1973505932","https://openalex.org/W2547355295","https://openalex.org/W2914442136","https://openalex.org/W2098851424","https://openalex.org/W2159053194"],"abstract_inverted_index":{"The":[0],"traditional":[1],"approach":[2],"to":[3,12,22,57],"FPGA":[4,30],"packing":[5,78],"and":[6,83,99],"CLB-level":[7],"placement":[8,41,71],"has":[9],"been":[10],"shown":[11],"yield":[13],"significantly":[14],"worse":[15],"quality":[16],"than":[17,107],"approaches":[18],"which":[19,36,62],"allow":[20],"BLEs":[21],"move":[23],"during":[24],"placement.":[25],"In":[26],"practice,":[27],"however,":[28],"modern":[29],"architectures":[31],"require":[32],"expensive":[33],"DRC":[34],"checks":[35],"can":[37],"render":[38],"full":[39],"BLE-level":[40,70],"impractical.":[42],"We":[43,75],"address":[44],"this":[45],"problem":[46],"by":[47],"proposing":[48],"a":[49],"novel":[50],"clustering":[51],"framework":[52],"that":[53,72,85],"uses":[54],"physical":[55],"information":[56],"produce":[58],"better":[59],"initial":[60],"packings":[61],"can,":[63],"in":[64],"turn,":[65],"reduce":[66],"the":[67],"amount":[68],"of":[69],"is":[73],"required.":[74],"quantify":[76],"our":[77],"technique":[79],"across":[80],"accepted":[81],"benchmarks":[82],"show":[84],"it":[86],"produces":[87],"results":[88],"with":[89],"16%":[90],"less":[91,101],"wire":[92],"length,":[93],"19%":[94],"smaller":[95],"minimum":[96],"channel":[97],"widths,":[98],"8%":[100],"critical":[102],"path":[103],"delay,":[104],"on":[105],"average,":[106],"leading":[108],"methods.":[109]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}