{"id":"https://openalex.org/W2107258133","doi":"https://doi.org/10.1109/fpl.2005.1515812","title":"High-throughput reconfigurable computing: design and implementation of an idea encryption cryptosystem on the SRC-6E reconfigurable computer","display_name":"High-throughput reconfigurable computing: design and implementation of an idea encryption cryptosystem on the SRC-6E reconfigurable computer","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2107258133","doi":"https://doi.org/10.1109/fpl.2005.1515812","mag":"2107258133"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515812","pdf_url":null,"source":null,"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030423086","display_name":"Allen Michalski","orcid":null},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Michalski","raw_affiliation_strings":["CSE Department, University of South Carolina, Columbia, SC, USA","Dept. of Comput. Sci. & Eng., South Carolina Univ., Columbia, SC, USA"],"affiliations":[{"raw_affiliation_string":"CSE Department, University of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., South Carolina Univ., Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031591405","display_name":"Duncan A. Buell","orcid":"https://orcid.org/0000-0002-4668-5848"},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Buell","raw_affiliation_strings":["CSE Department, University of South Carolina, Columbia, SC, USA","Dept. of Comput. Sci. & Eng., South Carolina Univ., Columbia, SC, USA"],"affiliations":[{"raw_affiliation_string":"CSE Department, University of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., South Carolina Univ., Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004924763","display_name":"Kris Gaj","orcid":"https://orcid.org/0000-0002-5050-8748"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Gaj","raw_affiliation_strings":["ECE Department, George Mason University, Fairfax, VA, USA","George Mason University"],"affiliations":[{"raw_affiliation_string":"ECE Department, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]},{"raw_affiliation_string":"George Mason University","institution_ids":["https://openalex.org/I162714631"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030423086"],"corresponding_institution_ids":["https://openalex.org/I155781252"],"apc_list":null,"apc_paid":null,"fwci":1.0312,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.78326956,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"681","last_page":"686"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.792930006980896},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7188268899917603},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6861661672592163},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6846535205841064},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6056724190711975},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5838814973831177},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5458775162696838},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.5100358128547668},{"id":"https://openalex.org/keywords/workstation","display_name":"Workstation","score":0.5089023113250732},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.49909257888793945},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.30301332473754883},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.27922964096069336},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23330333828926086}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.792930006980896},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7188268899917603},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6861661672592163},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6846535205841064},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6056724190711975},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5838814973831177},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5458775162696838},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.5100358128547668},{"id":"https://openalex.org/C67953723","wikidata":"https://www.wikidata.org/wiki/Q192525","display_name":"Workstation","level":2,"score":0.5089023113250732},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.49909257888793945},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.30301332473754883},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.27922964096069336},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23330333828926086},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2005.1515812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515812","pdf_url":null,"source":null,"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W329998640","https://openalex.org/W1599293419","https://openalex.org/W1605116544","https://openalex.org/W1686854917","https://openalex.org/W1989156803","https://openalex.org/W2150010995","https://openalex.org/W6636123720"],"related_works":["https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"The":[0],"combination":[1],"of":[2,18,76,96,122],"traditional":[3],"microprocessors":[4],"workstations":[5,19,34],"and":[6,90,102,111,116],"hardware-reconfigurable":[7],"field":[8],"programmable":[9],"gate":[10],"arrays":[11],"(FPGAs)":[12],"has":[13],"developed":[14],"a":[15,57,112,117],"new":[16,51],"class":[17],"known":[20],"as":[21,48],"reconfigurable":[22],"computers,":[23],"with":[24],"several":[25],"examples":[26],"demonstrating":[27],"significant":[28],"speedups":[29],"compared":[30,65],"to":[31,66],"standalone":[32],"PC":[33,43],"alone.":[35],"Several":[36],"platforms":[37],"implement":[38],"PC-FPGA":[39],"communication":[40,59],"using":[41,79],"common":[42],"peripheral":[44],"interface":[45,60],"buses":[46],"such":[47],"PCI-X.":[49],"A":[50],"approach":[52],"from":[53],"SRC":[54,81,83,107,115],"Computers":[55],"implements":[56],"highspeed":[58],"that":[61,86],"increases":[62],"the":[63,80,106],"throughput":[64,89],"PCI":[67],"interfaces.":[68],"This":[69],"paper":[70],"demonstrates":[71],"an":[72],"efficient":[73],"high-throughput":[74],"implementation":[75,121],"IDEA":[77,123],"encryption":[78],"platform.":[82],"design":[84],"choices":[85],"influence":[87],"both":[88],"area":[91],"are":[92,109,124],"evaluated.":[93],"Detailed":[94],"analyses":[95],"FPGA":[97],"resource":[98],"utilizations,":[99],"data":[100],"transfer":[101],"reconfiguration":[103],"overheads":[104],"for":[105],"system":[108],"provided,":[110],"comparison":[113],"between":[114],"public":[118],"domain":[119],"software":[120],"given.":[125]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}