{"id":"https://openalex.org/W2097808015","doi":"https://doi.org/10.1109/fpl.2005.1515803","title":"A novel toolset for the development of fpga-like reconfigurable logic","display_name":"A novel toolset for the development of fpga-like reconfigurable logic","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2097808015","doi":"https://doi.org/10.1109/fpl.2005.1515803","mag":"2097808015"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515803","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019555613","display_name":"Alexander Danilin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]},{"id":"https://openalex.org/I1329325741","display_name":"Philips (Finland)","ror":"https://ror.org/01g4jev56","country_code":"FI","type":"company","lineage":["https://openalex.org/I1329325741","https://openalex.org/I4210122849"]}],"countries":["FI","NL"],"is_corresponding":true,"raw_author_name":"A. Danilin","raw_affiliation_strings":["Philips Research Laboratories, Netherlands","Philips' Research Laboratories, Eindhoven-Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Netherlands","institution_ids":["https://openalex.org/I4210122849"]},{"raw_affiliation_string":"Philips' Research Laboratories, Eindhoven-Netherlands","institution_ids":["https://openalex.org/I1329325741"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107726119","display_name":"M. Bennebroek","orcid":null},"institutions":[{"id":"https://openalex.org/I1329325741","display_name":"Philips (Finland)","ror":"https://ror.org/01g4jev56","country_code":"FI","type":"company","lineage":["https://openalex.org/I1329325741","https://openalex.org/I4210122849"]},{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["FI","NL"],"is_corresponding":false,"raw_author_name":"M. Bennebroek","raw_affiliation_strings":["Philips Research Laboratories, Netherlands","Philips' Research Laboratories, Eindhoven-Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Netherlands","institution_ids":["https://openalex.org/I4210122849"]},{"raw_affiliation_string":"Philips' Research Laboratories, Eindhoven-Netherlands","institution_ids":["https://openalex.org/I1329325741"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110272995","display_name":"Sergei Sawitzki","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]},{"id":"https://openalex.org/I1329325741","display_name":"Philips (Finland)","ror":"https://ror.org/01g4jev56","country_code":"FI","type":"company","lineage":["https://openalex.org/I1329325741","https://openalex.org/I4210122849"]}],"countries":["FI","NL"],"is_corresponding":false,"raw_author_name":"S. Sawitzki","raw_affiliation_strings":["Philips Research Laboratories, Netherlands","Philips' Research Laboratories, Eindhoven-Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Netherlands","institution_ids":["https://openalex.org/I4210122849"]},{"raw_affiliation_string":"Philips' Research Laboratories, Eindhoven-Netherlands","institution_ids":["https://openalex.org/I1329325741"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5019555613"],"corresponding_institution_ids":["https://openalex.org/I1329325741","https://openalex.org/I4210122849"],"apc_list":null,"apc_paid":null,"fwci":1.8047,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.85565476,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3203","issue":null,"first_page":"640","last_page":"643"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7913122177124023},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6803950071334839},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6759060621261597},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6696574687957764},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.642076849937439},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5267353057861328},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.49436092376708984},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.49294257164001465},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4780878722667694},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.473568320274353},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.47108542919158936},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45882701873779297},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4500097930431366},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4270566999912262},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3365386426448822},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1572331190109253},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09882447123527527}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7913122177124023},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6803950071334839},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6759060621261597},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6696574687957764},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.642076849937439},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5267353057861328},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.49436092376708984},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.49294257164001465},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4780878722667694},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.473568320274353},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.47108542919158936},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45882701873779297},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4500097930431366},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4270566999912262},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3365386426448822},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1572331190109253},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09882447123527527},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2005.1515803","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W169456580","https://openalex.org/W1538071550","https://openalex.org/W1554946472","https://openalex.org/W1575153928","https://openalex.org/W1831088354","https://openalex.org/W2070392651","https://openalex.org/W2113645429","https://openalex.org/W2162546785","https://openalex.org/W4238617151","https://openalex.org/W4256464439","https://openalex.org/W6634288260"],"related_works":["https://openalex.org/W2014521732","https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2024574431","https://openalex.org/W2387100797","https://openalex.org/W2129019972","https://openalex.org/W3012528295","https://openalex.org/W2105249210","https://openalex.org/W1990901299"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,14,57,85,137,143],"toolset":[4,62,122],"to":[5,19,106,119,157],"develop":[6],"FPGA-like":[7,39],"reconfigurable":[8,24],"logic":[9,25],"which":[10],"is":[11,104,117,140],"optimized":[12,141],"towards":[13],"specific":[15],"application":[16],"domain.":[17],"Compared":[18],"existing":[20],"multi-domain":[21],"architectures,":[22],"domain-optimized":[23],"carry":[26],"much":[27],"lower":[28],"area":[29],"costs":[30],"and,":[31,90],"therefore,":[32],"might":[33],"drive":[34],"the":[35,52,67,78,107,121,125,128,133,148,153],"deployment":[36],"of":[37,54,69,127,136,145],"embedded":[38],"cores":[40],"in":[41,84],"integrated":[42],"circuits.":[43],"An":[44,115],"architectural":[45,70],"template":[46],"has":[47],"been":[48],"developed":[49,108],"that":[50,158],"enables":[51],"definition":[53],"components":[55],"with":[56],"virtually":[58],"unmatched":[59],"flexibility.":[60],"The":[61],"provides":[63],"fast":[64],"feedback":[65],"on":[66],"effect":[68],"changes":[71],"upon":[72],"mapping":[73],"results.":[74],"Once":[75],"satisfactory":[76],"optimized,":[77],"architecture":[79,110,139],"can":[80],"actually":[81],"be":[82],"implemented":[83],"selected":[86],"CMOS":[87],"process":[88],"technology":[89],"besides":[91],"soft-":[92],"and":[93,112,124,152],"hard-":[94],"cores,":[95],"patterns":[96],"for":[97,142],"manufacturing":[98],"test":[99],"are":[100],"generated.":[101],"Special":[102],"attention":[103],"given":[105],"graphical":[109],"editor":[111],"place-and-route":[113],"tool.":[114],"example":[116],"included":[118],"demonstrate":[120],"usage":[123],"advantages":[126],"flexible":[129],"component":[130],"definitions.":[131],"Here,":[132],"routing":[134],"network":[135],"simple":[138],"set":[144,151],"functions":[146],"from":[147],"MCNC":[149],"benchmark":[150],"result":[154],"compares":[155],"favorable":[156],"obtained":[159],"by":[160],"VPR.":[161]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
