{"id":"https://openalex.org/W2147464142","doi":"https://doi.org/10.1109/fpl.2005.1515795","title":"Implementation of ranking filters on general purpose and reconfigurable architecture based on high density FPGA devices","display_name":"Implementation of ranking filters on general purpose and reconfigurable architecture based on high density FPGA devices","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2147464142","doi":"https://doi.org/10.1109/fpl.2005.1515795","mag":"2147464142"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515795","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515795","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056611420","display_name":"Dragomir Milojevic","orcid":"https://orcid.org/0000-0001-5915-5160"},"institutions":[{"id":"https://openalex.org/I132053463","display_name":"Universit\u00e9 Libre de Bruxelles","ror":"https://ror.org/01r9htc13","country_code":"BE","type":"education","lineage":["https://openalex.org/I132053463"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"D. Milojevic","raw_affiliation_strings":["Services des Syst\u00e8mes Logiqus et Num\u00e9riques, Universit\u00e9 Libre de Bruxelles, Brussels, Belgium","Service des Systemes Logiques et Numeriques, Univ. Libre de Bruxelles, Belgium"],"affiliations":[{"raw_affiliation_string":"Services des Syst\u00e8mes Logiqus et Num\u00e9riques, Universit\u00e9 Libre de Bruxelles, Brussels, Belgium","institution_ids":["https://openalex.org/I132053463"]},{"raw_affiliation_string":"Service des Systemes Logiques et Numeriques, Univ. Libre de Bruxelles, Belgium","institution_ids":["https://openalex.org/I132053463"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5056611420"],"corresponding_institution_ids":["https://openalex.org/I132053463"],"apc_list":null,"apc_paid":null,"fwci":0.4567,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.76268709,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"q4","issue":null,"first_page":"602","last_page":"605"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.978600025177002,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.978600025177002,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10820","display_name":"Fuzzy Logic and Control Systems","score":0.9678000211715698,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.954200029373169,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.9014536142349243},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7933429479598999},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7142505645751953},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6888557076454163},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6842207312583923},{"id":"https://openalex.org/keywords/ranking","display_name":"Ranking (information retrieval)","score":0.5628793835639954},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5114032626152039},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5007612705230713},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4872190058231354},{"id":"https://openalex.org/keywords/rank","display_name":"Rank (graph theory)","score":0.4394637942314148},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3968481421470642},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3634156584739685},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17420712113380432},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09893670678138733},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09353408217430115}],"concepts":[{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.9014536142349243},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7933429479598999},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7142505645751953},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6888557076454163},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6842207312583923},{"id":"https://openalex.org/C189430467","wikidata":"https://www.wikidata.org/wiki/Q7293293","display_name":"Ranking (information retrieval)","level":2,"score":0.5628793835639954},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5114032626152039},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5007612705230713},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4872190058231354},{"id":"https://openalex.org/C164226766","wikidata":"https://www.wikidata.org/wiki/Q7293202","display_name":"Rank (graph theory)","level":2,"score":0.4394637942314148},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3968481421470642},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3634156584739685},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17420712113380432},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09893670678138733},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09353408217430115},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2005.1515795","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515795","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:dipot.ulb.ac.be:2013/74284","is_oa":false,"landing_page_url":"http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/74284","pdf_url":null,"source":{"id":"https://openalex.org/S4306401063","display_name":"D\u00e9p\u00f4t institutionnel de l'Universit\u00e9 libre de Bruxelles (Universit\u00e9 Libre de Bruxelles)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I132053463","host_organization_name":"Universit\u00e9 Libre de Bruxelles","host_organization_lineage":["https://openalex.org/I132053463"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"In: Field Programmable Logic and Applications, 2005. International Conference on","raw_type":"info:ulb-repo/semantics/openurl/proceeding"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1569033989","https://openalex.org/W2027992898","https://openalex.org/W2041002007","https://openalex.org/W2049399962","https://openalex.org/W2086509021","https://openalex.org/W2112004886","https://openalex.org/W2143421755","https://openalex.org/W2154373645","https://openalex.org/W2497626200","https://openalex.org/W4285719527","https://openalex.org/W6723890852"],"related_works":["https://openalex.org/W1597195064","https://openalex.org/W2915007006","https://openalex.org/W2129938370","https://openalex.org/W3164835776","https://openalex.org/W2230641373","https://openalex.org/W4240478293","https://openalex.org/W1654177473","https://openalex.org/W4237657704","https://openalex.org/W2167857335","https://openalex.org/W3160516639"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3,16,29,54],"present":[4],"the":[5,37,47,93],"implementation":[6],"of":[7,61,77],"ranking":[8],"filters":[9],"on":[10,23,46],"two":[11],"different":[12],"computer":[13,21],"architectures.":[14],"First":[15],"consider":[17,55],"a":[18,56,70],"general":[19,95],"purpose":[20,96],"based":[22],"Intel":[24],"Pentium":[25],"4":[26],"microprocessor":[27],"and":[28,50,67],"show":[30],"that":[31],"when":[32],"SSE2":[33],"extension":[34],"is":[35,86],"used":[36],"throughput":[38,76],"vary":[39],"from":[40,81],"20":[41],"to":[42,83,88],"200":[43],"MB/sec,":[44],"depending":[45],"neighborhood":[48],"size":[49],"rank":[51],"value.":[52],"Secondly,":[53],"reconfigurable":[57],"architecture":[58],"using":[59],"hundreds":[60],"processing":[62],"elements":[63],"running":[64],"bit-serial":[65],"algorithms":[66],"implemented":[68],"in":[69],"high":[71],"density":[72],"FPGA":[73],"device.":[74],"The":[75],"such":[78],"system":[79],"varies":[80],"900":[82],"2600MB/sec":[84],"which":[85],"13":[87],"40":[89],"times":[90],"faster":[91],"than":[92],"considered":[94],"architecture.":[97]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
