{"id":"https://openalex.org/W2148912862","doi":"https://doi.org/10.1109/fpl.2005.1515782","title":"FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach","display_name":"FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2148912862","doi":"https://doi.org/10.1109/fpl.2005.1515782","mag":"2148912862"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"J. Javier Martinez","orcid":null},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Javier Martinez","raw_affiliation_strings":["Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain","institution_ids":["https://openalex.org/I3123212020"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015593559","display_name":"F. Javier Toledo","orcid":"https://orcid.org/0000-0002-5277-9322"},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"E. Javier Toledo","raw_affiliation_strings":["Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain","institution_ids":["https://openalex.org/I3123212020"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011862833","display_name":"E. Javier Garrigos","orcid":null},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"E. Javier Garrigos","raw_affiliation_strings":["Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain","institution_ids":["https://openalex.org/I3123212020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111962357","display_name":"J. Manuel Ferrdndez","orcid":null},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Manuel Ferrdndez","raw_affiliation_strings":["Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dpto. Electr\u00f3nica Tecnolog\u00eda, de Computadoras y Proyectos, Universidad Polit\u00e9cnica de Cartagena, Cartagena, Spain","institution_ids":["https://openalex.org/I3123212020"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I3123212020"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"547","last_page":"550"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8617087006568909},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7748751640319824},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.640127420425415},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6077600121498108},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5948709845542908},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.5159181356430054},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47918522357940674},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47010868787765503},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43521153926849365},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11661180853843689}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8617087006568909},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7748751640319824},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.640127420425415},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6077600121498108},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5948709845542908},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.5159181356430054},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47918522357940674},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47010868787765503},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43521153926849365},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11661180853843689},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2005.1515782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2121914493","https://openalex.org/W2150872535","https://openalex.org/W2153625893","https://openalex.org/W2160160584","https://openalex.org/W2612977034"],"related_works":["https://openalex.org/W2022544890","https://openalex.org/W2394097730","https://openalex.org/W2475378634","https://openalex.org/W2111241003","https://openalex.org/W2113405914","https://openalex.org/W4312353617","https://openalex.org/W4387951306","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"an":[5,50,61,70],"area-time":[6],"efficient":[7],"architecture":[8,66],"for":[9],"the":[10,19,36,64,84],"realization":[11],"of":[12,79,86],"self-clocked":[13],"MAC":[14],"filters":[15],"on":[16,41,69],"FPGA.":[17],"First,":[18],"self-timed":[20],"4-phase":[21],"oscillator/counter":[22],"is":[23,44,67],"analyzed":[24],"and":[25,46,56,72],"characterized,":[26],"showing":[27],"experimental":[28],"results":[29],"in":[30],"comparison":[31],"with":[32,74],"simulation":[33],"foreseen.":[34],"Next,":[35],"proposed":[37,65],"filter":[38,78],"architecture,":[39],"based":[40],"circular":[42],"memories,":[43],"described":[45],"efficiently":[47],"implemented":[48,68],"as":[49],"IP":[51,77],"module":[52],"using":[53,63],"device":[54],"primitives":[55],"relative":[57],"location":[58],"constraints.":[59],"Finally,":[60],"example":[62],"FPGA":[71],"compared":[73],"a":[75],"standard":[76],"similar":[80],"characteristics,":[81],"pointing":[82],"out":[83],"advantages":[85],"our":[87],"approach.":[88]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
