{"id":"https://openalex.org/W2117199130","doi":"https://doi.org/10.1109/fpl.2005.1515772","title":"A run-time reconfigurable hardware infrastructure for IP-core evaluation and test","display_name":"A run-time reconfigurable hardware infrastructure for IP-core evaluation and test","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2117199130","doi":"https://doi.org/10.1109/fpl.2005.1515772","mag":"2117199130"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087135888","display_name":"R. Siripokarpirom","orcid":null},"institutions":[{"id":"https://openalex.org/I884043246","display_name":"Hamburg University of Technology","ror":"https://ror.org/04bs1pb34","country_code":"DE","type":"education","lineage":["https://openalex.org/I884043246"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"R. Siripokarpirom","raw_affiliation_strings":["Department of Distributed Systems, Technical University Hamburg-Harburg, Germany","Dept. of Distributed Syst., Tech. Univ. Hamburg-Harburg, Hamburg, Germany"],"affiliations":[{"raw_affiliation_string":"Department of Distributed Systems, Technical University Hamburg-Harburg, Germany","institution_ids":["https://openalex.org/I884043246"]},{"raw_affiliation_string":"Dept. of Distributed Syst., Tech. Univ. Hamburg-Harburg, Hamburg, Germany","institution_ids":["https://openalex.org/I884043246"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5087135888"],"corresponding_institution_ids":["https://openalex.org/I884043246"],"apc_list":null,"apc_paid":null,"fwci":0.2578,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59173044,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"505","last_page":"508"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8754680752754211},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7722263336181641},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7644602060317993},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7441378831863403},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7345394492149353},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7168177366256714},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7074435949325562},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5526236295700073},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5254135131835938},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4885019063949585},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.4496850371360779},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41134870052337646},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2340792417526245}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8754680752754211},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7722263336181641},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7644602060317993},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7441378831863403},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7345394492149353},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7168177366256714},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7074435949325562},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5526236295700073},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5254135131835938},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4885019063949585},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.4496850371360779},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41134870052337646},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2340792417526245},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2005.1515772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W157706557","https://openalex.org/W1589372958","https://openalex.org/W2028504835","https://openalex.org/W2156253418","https://openalex.org/W6606411226"],"related_works":["https://openalex.org/W2170071008","https://openalex.org/W2103996454","https://openalex.org/W3029775214","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2001552871","https://openalex.org/W1974143443","https://openalex.org/W2353557016","https://openalex.org/W2129151116","https://openalex.org/W2133965417"],"abstract_inverted_index":{"In":[0],"recent":[1],"years,":[2],"there":[3],"has":[4],"been":[5],"increasing":[6],"interest":[7],"in":[8,97],"exploiting":[9],"the":[10,36,40,63,91,95,109,118],"partial":[11],"and":[12,22,46,69,111],"run-time":[13,37,66],"reconfiguration":[14],"of":[15,39,44,50,113,117],"FPGAs":[16,45],"to":[17,59,88,107],"develop":[18],"novel":[19],"computing":[20],"systems":[21],"applications.":[23],"This":[24],"paper":[25],"proposes":[26],"a":[27,48,78,98,114],"generic,":[28],"reusable":[29],"FPGA-based":[30],"test":[31],"platform":[32,73],"that":[33],"relies":[34],"on":[35],"reconfigurability":[38],"Xilinx":[41],"Virtex":[42],"family":[43],"allows":[47],"number":[49],"hardware":[51,64,92],"components":[52],"such":[53],"as":[54],"Intellectual":[55],"Property":[56],"(IP)":[57],"cores":[58],"be":[60,75],"loaded":[61],"into":[62,77],"during":[65],"for":[67],"testing":[68],"evaluation":[70],"purposes.":[71],"The":[72],"can":[74],"incorporated":[76],"software-based":[79],"simulation":[80],"environment,":[81],"thus":[82],"allowing":[83],"software":[84],"models":[85],"or":[86],"testbenches":[87],"interact":[89],"with":[90],"modules":[93],"inside":[94],"FPGA":[96],"co-simulation/emulation":[99],"manner.":[100],"A":[101],"case":[102],"study":[103],"is":[104],"also":[105],"given":[106],"demonstrate":[108],"practicality":[110],"correctness":[112],"proof-of-concept":[115],"implementation":[116],"proposed":[119],"platform.":[120]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}