{"id":"https://openalex.org/W2121381243","doi":"https://doi.org/10.1109/fpl.2005.1515766","title":"An emulation model for sequential ATPG-based bounded model checking","display_name":"An emulation model for sequential ATPG-based bounded model checking","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2121381243","doi":"https://doi.org/10.1109/fpl.2005.1515766","mag":"2121381243"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002643397","display_name":"Qiang Qiang","orcid":"https://orcid.org/0000-0002-9071-3236"},"institutions":[{"id":"https://openalex.org/I58956616","display_name":"Case Western Reserve University","ror":"https://ror.org/051fd9666","country_code":"US","type":"education","lineage":["https://openalex.org/I58956616"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Qiang Qiang","raw_affiliation_strings":["Elec. Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA"],"affiliations":[{"raw_affiliation_string":"Elec. Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021334492","display_name":"D.G. Saab","orcid":null},"institutions":[{"id":"https://openalex.org/I58956616","display_name":"Case Western Reserve University","ror":"https://ror.org/051fd9666","country_code":"US","type":"education","lineage":["https://openalex.org/I58956616"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.G. Saab","raw_affiliation_strings":["Elec. Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA"],"affiliations":[{"raw_affiliation_string":"Elec. Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016021239","display_name":"Fatih Kocan","orcid":null},"institutions":[{"id":"https://openalex.org/I178169726","display_name":"Southern Methodist University","ror":"https://ror.org/042tdr378","country_code":"US","type":"education","lineage":["https://openalex.org/I178169726"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Kocan","raw_affiliation_strings":["Comp. Sci. and Engr., Southern Methodist University, Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"Comp. Sci. and Engr., Southern Methodist University, Dallas, TX, USA","institution_ids":["https://openalex.org/I178169726"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Abraham","raw_affiliation_strings":["Comp. Engr. Research Center, University of Texas, Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Comp. Engr. Research Center, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5002643397"],"corresponding_institution_ids":["https://openalex.org/I58956616"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1861182,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1304","issue":null,"first_page":"469","last_page":"474"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8294296860694885},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7290590405464172},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7279854416847229},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.6410948038101196},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5468546748161316},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.50026535987854},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.45690882205963135},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4343807101249695},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4242391288280487},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42172113060951233},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.4173533320426941},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3609810173511505},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.350384920835495},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24924376606941223},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11591541767120361},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09929606318473816},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0924939513206482},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07431498169898987}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8294296860694885},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7290590405464172},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7279854416847229},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.6410948038101196},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5468546748161316},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.50026535987854},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.45690882205963135},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4343807101249695},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4242391288280487},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42172113060951233},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.4173533320426941},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3609810173511505},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.350384920835495},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24924376606941223},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11591541767120361},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09929606318473816},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0924939513206482},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07431498169898987},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2005.1515766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1493721853","https://openalex.org/W1506034564","https://openalex.org/W1554885925","https://openalex.org/W1848667534","https://openalex.org/W1903629970","https://openalex.org/W1973801604","https://openalex.org/W2021492392","https://openalex.org/W2049443371","https://openalex.org/W2120271505","https://openalex.org/W2149107969","https://openalex.org/W2158246429","https://openalex.org/W4236292970","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2163047760","https://openalex.org/W2955439067","https://openalex.org/W1519923721","https://openalex.org/W3147676363"],"abstract_inverted_index":{"Bounded":[0],"model":[1],"checking":[2],"based":[3],"on":[4,40,58],"sequential":[5,14],"ATPG":[6,15],"(automatic":[7],"test":[8],"pattern":[9],"generation)":[10],"is":[11,21,70],"virtually":[12],"the":[13,37,56],"state-justification":[16,19,57],"phase.":[17],"The":[18,61],"phase":[20],"a":[22,51],"very":[23],"complicated":[24],"and":[25],"expensive":[26],"process":[27],"in":[28],"term":[29],"of":[30,63,67],"CPU":[31],"time.":[32],"Previous":[33],"work":[34],"to":[35,43,54,72],"speed":[36],"search":[38],"concentrated":[39],"developing":[41],"heuristics":[42],"achieve":[44,73],"speed-up.":[45,74],"In":[46],"this":[47],"paper":[48],"we":[49],"develop":[50],"novel":[52],"architecture":[53],"emulate":[55],"reconfigurable":[59,68],"hardware.":[60],"feature":[62],"fine-grain":[64],"massive":[65],"parallelism":[66],"hardware":[69],"exploited":[71]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
