{"id":"https://openalex.org/W2161640626","doi":"https://doi.org/10.1109/fpl.2005.1515759","title":"Architecture-adaptive routability-driven placement for FPGAs","display_name":"Architecture-adaptive routability-driven placement for FPGAs","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2161640626","doi":"https://doi.org/10.1109/fpl.2005.1515759","mag":"2161640626"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515759","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102963360","display_name":"Akshay Sharma","orcid":"https://orcid.org/0000-0003-4896-8726"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Sharma","raw_affiliation_strings":["Department of Electrical Engineering, University of Washington, Seattle, WA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003894282","display_name":"Scott Hauck","orcid":"https://orcid.org/0000-0001-9516-0311"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Hauck","raw_affiliation_strings":["Department of Electrical Engineering, University of Washington, Seattle, WA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032101034","display_name":"Carl Ebeling","orcid":"https://orcid.org/0000-0001-5032-3615"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Ebeling","raw_affiliation_strings":["Department of Computer Science and Engineering, University of Washington, Seattle, WA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5102963360"],"corresponding_institution_ids":["https://openalex.org/I201448701"],"apc_list":null,"apc_paid":null,"fwci":6.4024,"has_fulltext":false,"cited_by_count":39,"citation_normalized_percentile":{"value":0.96794886,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"427","last_page":"432"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8710156679153442},{"id":"https://openalex.org/keywords/adaptability","display_name":"Adaptability","score":0.6586246490478516},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6072835922241211},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.580123245716095},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5482460260391235},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5291096568107605},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5151992440223694},{"id":"https://openalex.org/keywords/independence","display_name":"Independence (probability theory)","score":0.47713422775268555},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.4732276201248169},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.4692521095275879},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4187981188297272},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39536669850349426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24794992804527283},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.10523906350135803},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08841535449028015},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.07789334654808044}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8710156679153442},{"id":"https://openalex.org/C177606310","wikidata":"https://www.wikidata.org/wiki/Q5674297","display_name":"Adaptability","level":2,"score":0.6586246490478516},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6072835922241211},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.580123245716095},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5482460260391235},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5291096568107605},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5151992440223694},{"id":"https://openalex.org/C35651441","wikidata":"https://www.wikidata.org/wiki/Q625303","display_name":"Independence (probability theory)","level":2,"score":0.47713422775268555},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.4732276201248169},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.4692521095275879},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4187981188297272},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39536669850349426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24794992804527283},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.10523906350135803},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08841535449028015},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.07789334654808044},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2005.1515759","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1537490912","https://openalex.org/W1594570581","https://openalex.org/W1966573088","https://openalex.org/W1978599303","https://openalex.org/W1985146356","https://openalex.org/W1992393251","https://openalex.org/W2024060531","https://openalex.org/W2062435236","https://openalex.org/W2090068045","https://openalex.org/W2094806828","https://openalex.org/W2109656299","https://openalex.org/W2138438526","https://openalex.org/W2139637699","https://openalex.org/W2142490124","https://openalex.org/W2144927107","https://openalex.org/W2148535958","https://openalex.org/W2152475379","https://openalex.org/W2154678818","https://openalex.org/W2160007289","https://openalex.org/W2163599210","https://openalex.org/W2164654367","https://openalex.org/W2168019708","https://openalex.org/W2275304190","https://openalex.org/W2752885492","https://openalex.org/W4232904085","https://openalex.org/W4246775085","https://openalex.org/W6676280906"],"related_works":["https://openalex.org/W2138311189","https://openalex.org/W3183044703","https://openalex.org/W1968931833","https://openalex.org/W4245174233","https://openalex.org/W2122425352","https://openalex.org/W108855261","https://openalex.org/W2098132017","https://openalex.org/W4244167835","https://openalex.org/W2031837447","https://openalex.org/W2007503867"],"abstract_inverted_index":{"Current":[0],"FPGA":[1,57,85,101,155],"placement":[2,9,24,58,79],"algorithms":[3],"estimate":[4],"the":[5,50,65,113,122,130],"routability":[6,18],"of":[7,15,32,46,52,64,90,112,121,124,139],"a":[8,30,53,69,76,99,105],"using":[10,16],"architecture-specific":[11,17],"metrics.":[12],"The":[13,44,62,88,110],"shortcoming":[14],"estimates":[19],"is":[20,27,49,68,118],"limited":[21],"adaptability.":[22],"A":[23],"algorithm":[25,59,67,80],"that":[26,73,146],"targeted":[28],"to":[29,41,96],"class":[31],"architecturally":[33],"similar":[34],"FPGAs":[35],"may":[36],"not":[37],"be":[38],"easily":[39],"adapted":[40],"other":[42],"architectures.":[43,156],"subject":[45],"this":[47],"paper":[48],"development":[51],"routability-driven":[54],"architecture":[55,83,102,108],"adaptive":[56,84],"called":[60],"Independence.":[61],"core":[63],"Independence":[66,117,147],"simultaneous":[70],"place-and-route":[71],"approach":[72],"tightly":[74],"couples":[75],"simulated":[77],"annealing":[78],"with":[81],"an":[82],"router":[86],"(Pathfinder).":[87],"results":[89,144],"our":[91,143],"experiments":[92],"demonstrate":[93],"Independence's":[94],"adaptability":[95],"island-style":[97,154],"FPGAs,":[98],"hierarchical":[100],"(HSRA),":[103],"and":[104,136],"coarse-grained":[106],"reconfigurable":[107],"(RaPiD).":[109],"quality":[111,123],"placements":[114,131,151],"produced":[115,132],"by":[116,133],"within":[119,137],"1.2%":[120],"VPRs":[125],"placements.":[126],"17%":[127],"better":[128],"than":[129],"HSRA's":[134],"placer,":[135],"0.7%":[138],"RaPiD's":[140],"placer.":[141],"Further,":[142],"show":[145],"produces":[148],"clearly":[149],"superior":[150],"on":[152],"routing-poor":[153]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
