{"id":"https://openalex.org/W2130146997","doi":"https://doi.org/10.1109/fpl.2005.1515755","title":"On the reliability evaluation of sram-based FPGA designs","display_name":"On the reliability evaluation of sram-based FPGA designs","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2130146997","doi":"https://doi.org/10.1109/fpl.2005.1515755","mag":"2130146997"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515755","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515755","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048586688","display_name":"Olivier H\u00e9ron","orcid":"https://orcid.org/0009-0007-0354-1522"},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"O. Heron","raw_affiliation_strings":["Institut f\u00fcr Technische Informatik, Universit\u00e4t Stuttgart, Germany","Inst. fur Technische Informatik, Univ. Stuttgart, Germany"],"affiliations":[{"raw_affiliation_string":"Institut f\u00fcr Technische Informatik, Universit\u00e4t Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]},{"raw_affiliation_string":"Inst. fur Technische Informatik, Univ. Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073486195","display_name":"Talal Arnaout","orcid":null},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"T. Arnaout","raw_affiliation_strings":["Institut f\u00fcr Technische Informatik, Universit\u00e4t Stuttgart, Germany","Inst. fur Technische Informatik, Univ. Stuttgart, Germany"],"affiliations":[{"raw_affiliation_string":"Institut f\u00fcr Technische Informatik, Universit\u00e4t Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]},{"raw_affiliation_string":"Inst. fur Technische Informatik, Univ. Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008775226","display_name":"Hans-Joachim Wunderlich","orcid":"https://orcid.org/0000-0003-4536-8290"},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"H. Wunderlich","raw_affiliation_strings":["Institut f\u00fcr Technische Informatik, Universit\u00e4t Stuttgart, Germany","Inst. fur Technische Informatik, Univ. Stuttgart, Germany"],"affiliations":[{"raw_affiliation_string":"Institut f\u00fcr Technische Informatik, Universit\u00e4t Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]},{"raw_affiliation_string":"Inst. fur Technische Informatik, Univ. Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048586688"],"corresponding_institution_ids":["https://openalex.org/I100066346"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.19257811,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"403","last_page":"408"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8569718599319458},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7758052349090576},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7605782747268677},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.605965256690979},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6005695462226868},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5985954403877258},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4921237826347351},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29021158814430237},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1977158784866333}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8569718599319458},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7758052349090576},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7605782747268677},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.605965256690979},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6005695462226868},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5985954403877258},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4921237826347351},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29021158814430237},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1977158784866333},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/fpl.2005.1515755","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515755","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.67.4128","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.67.4128","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ra.informatik.uni-stuttgart.de/research/publications/FPL05Paper.pdf","raw_type":"text"},{"id":"pmh:oai:informatik.uni-stuttgart.de:INPROC-2005-113","is_oa":false,"landing_page_url":"http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-113&amp;engl=1","pdf_url":null,"source":{"id":"https://openalex.org/S4306401306","display_name":"Fachbereich Informatik (University of Stuttgart)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100066346","host_organization_name":"University of Stuttgart","host_organization_lineage":["https://openalex.org/I100066346"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"\\n            In: IEEE Computer Society (ed.): Proceedings of the 15th IEEE\\n            International Conference on Field Programmable Logic and\\n            Applications (FPL), Tampere, Finland, August 24-26, 2005, pp.\\n            403-408\\n          ","raw_type":"Text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W23158330","https://openalex.org/W119808069","https://openalex.org/W1480045349","https://openalex.org/W1519752471","https://openalex.org/W1543784493","https://openalex.org/W1625650886","https://openalex.org/W2074673023","https://openalex.org/W2099329957","https://openalex.org/W2124403117","https://openalex.org/W2135225513","https://openalex.org/W2136658794","https://openalex.org/W2143974498","https://openalex.org/W2153066308","https://openalex.org/W2153887537","https://openalex.org/W2169164501","https://openalex.org/W2170564220","https://openalex.org/W4205461305","https://openalex.org/W4243891218","https://openalex.org/W4251792943","https://openalex.org/W4285719527","https://openalex.org/W6632701699"],"related_works":["https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W4399458808","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248","https://openalex.org/W2367794224","https://openalex.org/W2072850836"],"abstract_inverted_index":{"Benefits":[0],"of":[1,12,29,33,47,88],"field":[2],"programmable":[3],"gate":[4],"arrays":[5],"(FPGAs)":[6],"have":[7],"lead":[8],"to":[9,18,25,37,43,79,84],"a":[10,65,75],"spectrum":[11],"use":[13],"ranging":[14],"from":[15],"consumer":[16],"products":[17],"astronautics.":[19],"This":[20,72],"diversity":[21],"necessitates":[22],"the":[23,27,30,44,86],"need":[24],"evaluate":[26,80],"reliability":[28,87],"FPGA,":[31],"because":[32],"their":[34],"high":[35,45],"susceptibility":[36],"soft":[38],"errors,":[39],"which":[40,62],"are":[41],"due":[42],"density":[46],"embedded":[48],"SRAM":[49],"cells.":[50],"Reliability":[51],"evaluation":[52],"is":[53],"an":[54],"important":[55],"step":[56],"in":[57,64,69],"designing":[58],"highly":[59],"reliable":[60],"systems,":[61],"results":[63],"strong":[66],"competitive":[67],"advantage":[68],"today's":[70],"marketplace.":[71],"paper":[73],"proposes":[74],"mathematical":[76],"model":[77],"able":[78],"and":[81],"therefore":[82],"help":[83],"improve":[85],"SRAM-based":[89],"FPGAs.":[90]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":5}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
