{"id":"https://openalex.org/W2154900953","doi":"https://doi.org/10.1109/fpl.2005.1515739","title":"A verilog RTL synthesis tool for heterogeneous FPGAs","display_name":"A verilog RTL synthesis tool for heterogeneous FPGAs","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2154900953","doi":"https://doi.org/10.1109/fpl.2005.1515739","mag":"2154900953"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515739","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515739","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002356859","display_name":"Peter Jamieson","orcid":"https://orcid.org/0000-0002-3741-0201"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"P. Jamieson","raw_affiliation_strings":["Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090184149","display_name":"Jonathan Rose","orcid":"https://orcid.org/0000-0002-3551-2175"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Rose","raw_affiliation_strings":["Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5002356859"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":2.6388,"has_fulltext":false,"cited_by_count":43,"citation_normalized_percentile":{"value":0.90195675,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"305","last_page":"310"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8959541320800781},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8430277109146118},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7329599261283875},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6566176414489746},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.5536426901817322},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5410043597221375},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5170534253120422},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5011892318725586},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4845382571220398},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.47791892290115356},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.46005862951278687},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.426523357629776},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42069441080093384},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.1980440318584442},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17535898089408875},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12616783380508423},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.09220248460769653}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8959541320800781},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8430277109146118},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7329599261283875},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6566176414489746},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.5536426901817322},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5410043597221375},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5170534253120422},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5011892318725586},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4845382571220398},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.47791892290115356},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.46005862951278687},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.426523357629776},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42069441080093384},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.1980440318584442},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17535898089408875},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12616783380508423},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.09220248460769653},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2005.1515739","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515739","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.77.3289","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.77.3289","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~jayar/pubs/jamieson/jamiesonfpl05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W19494811","https://openalex.org/W1514336338","https://openalex.org/W1545343273","https://openalex.org/W1978998136","https://openalex.org/W1979269278","https://openalex.org/W2022341273","https://openalex.org/W2052076636","https://openalex.org/W2080267935","https://openalex.org/W2103883199","https://openalex.org/W2106290133","https://openalex.org/W2111488604","https://openalex.org/W2111911282","https://openalex.org/W2120428980","https://openalex.org/W2120763018","https://openalex.org/W2134152592","https://openalex.org/W2134262422","https://openalex.org/W2163847543","https://openalex.org/W2167328871","https://openalex.org/W4233492914","https://openalex.org/W4236875804","https://openalex.org/W4244690874","https://openalex.org/W4285719527","https://openalex.org/W6600777229"],"related_works":["https://openalex.org/W2005854230","https://openalex.org/W2168113051","https://openalex.org/W2090808187","https://openalex.org/W1748531671","https://openalex.org/W2121863986","https://openalex.org/W4241206086","https://openalex.org/W2081132365","https://openalex.org/W2142474790","https://openalex.org/W1964556228","https://openalex.org/W2325947006"],"abstract_inverted_index":{"Modern":[0],"heterogeneous":[1,78],"FPGAs":[2],"contain":[3],"\"hard\"":[4],"specific-purpose":[5],"structures":[6,27,58,103],"such":[7],"as":[8],"blocks":[9],"of":[10,55,101,133,155],"memory":[11],"and":[12,23,38,49,81,94,118,143],"multipliers":[13],"in":[14,35,59,104],"addition":[15],"to":[16,51,66,110,129,137],"the":[17,53,60,72,119,131,153],"completely":[18],"flexible":[19,69,99],"\"soft\"":[20],"programmable":[21],"logic":[22],"routing.":[24],"These":[25],"hard":[26,102],"provide":[28],"major":[29],"benefits,":[30],"yet":[31],"raise":[32],"interesting":[33],"questions":[34],"FPGA":[36,79,113],"CAD":[37,43,80,114,122],"architecture.":[39],"To":[40],"develop":[41],"high-quality":[42],"mapping":[44,146],"algorithms":[45],"for":[46,148],"these":[47],"structures,":[48],"indeed":[50],"measure":[52],"quality":[54,132,154],"proposed":[56],"new":[57],"architectural":[61],"domain,":[62],"it":[63],"is":[64],"essential":[65],"have":[67,125],"a":[68,89],"tool":[70,135],"at":[71],"RTL":[73],"synthesis":[74,90,141],"level":[75],"that":[76,97,151],"permits":[77,98],"architecture":[82],"experimentation.":[83],"In":[84],"this":[85,134],"paper":[86],"we":[87,144],"present":[88,145],"tool,":[91,142],"called":[92],"Odin,":[93],"an":[95,138],"algorithm":[96],"targeting":[100],"FPGAs.":[105],"Odin":[106],"maps":[107],"Verilog":[108],"designs":[109],"two":[111],"different":[112],"flows:":[115],"Altera's":[116],"Quartus,":[117],"academic":[120],"VPR":[121],"flow.":[123],"We":[124],"expended":[126],"significant":[127],"effort":[128],"make":[130],"comparable":[136],"industrial":[139],"front-end":[140],"results":[147],"our":[149,156],"benchmarks":[150],"show":[152],"results.":[157]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
