{"id":"https://openalex.org/W2131153388","doi":"https://doi.org/10.1109/fpl.2005.1515737","title":"A programmable logic architecture for prototyping clockless circuits","display_name":"A programmable logic architecture for prototyping clockless circuits","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2131153388","doi":"https://doi.org/10.1109/fpl.2005.1515737","mag":"2131153388"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515737","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038428972","display_name":"Laurent Fesquet","orcid":"https://orcid.org/0000-0002-6045-8510"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"L. Fesquet","raw_affiliation_strings":["TIMA Laboratory, France","TIMA Lab., Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017617798","display_name":"Marc Renaudin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M. Renaudin","raw_affiliation_strings":["TIMA Laboratory, France","TIMA Lab., Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038428972"],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":1.0882,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.80220267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"uucs 97 13","issue":null,"first_page":"293","last_page":"298"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.736743688583374},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7195137143135071},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6726809740066528},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6585165858268738},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6112192869186401},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5440123081207275},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5191054344177246},{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.5188509225845337},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.4746549725532532},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.47187891602516174},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4340997636318207},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.307361900806427},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19454559683799744},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11221280694007874},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07333013415336609},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.06773215532302856}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.736743688583374},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7195137143135071},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6726809740066528},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6585165858268738},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6112192869186401},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5440123081207275},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5191054344177246},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.5188509225845337},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.4746549725532532},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.47187891602516174},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4340997636318207},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.307361900806427},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19454559683799744},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11221280694007874},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07333013415336609},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.06773215532302856},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2005.1515737","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00104360v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00104360","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"15th International Conference on Field Programmable Logic & Applications (FPL'05), 2005, Tampere, Finland. pp.293- 298, ⟨10.1109/FPL.2005.1515737⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.5899999737739563,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W122486620","https://openalex.org/W1514480347","https://openalex.org/W1546435617","https://openalex.org/W1651903856","https://openalex.org/W2084517978","https://openalex.org/W2104105510","https://openalex.org/W2108454771","https://openalex.org/W2132339613","https://openalex.org/W2146127897","https://openalex.org/W2156947018","https://openalex.org/W2169788109","https://openalex.org/W2338366394","https://openalex.org/W2544832035","https://openalex.org/W4231905827","https://openalex.org/W6604992771","https://openalex.org/W6680056528"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W1511802890","https://openalex.org/W1553835358","https://openalex.org/W1607849496","https://openalex.org/W2972060505","https://openalex.org/W2994343469","https://openalex.org/W2102777336","https://openalex.org/W3105918491"],"abstract_inverted_index":{"This":[0,143],"paper":[1],"presents":[2],"a":[3,127,148],"novel":[4],"programmable":[5,108],"logic":[6,63,66,74,100,118,136,162],"device":[7],"(PLD)":[8],"architecture":[9,59,83,105,141],"for":[10],"implementing":[11],"and":[12,39,64,120,157],"prototyping":[13,159],"various":[14],"styles":[15,119,134],"of":[16,23,48,81,135,160],"clockless":[17],"or":[18],"asynchronous":[19,24,62,73,99,121,163],"circuits.":[20,164],"Many":[21],"classes":[22],"circuits":[25],"exist,":[26],"depending":[27],"on":[28],"the":[29,36,40,54,57,65,69,89,104,139,155,158],"timing":[30],"assumptions":[31],"that":[32],"are":[33,75,84],"made":[34],"at":[35],"logical":[37],"level":[38],"adopted":[41],"handshake":[42],"communication":[43],"protocols.":[44],"The":[45,78,107],"main":[46],"objective":[47],"this":[49,82],"work":[50,144],"is":[51,91,110,145],"to":[52,61,72,94,103,113,137,154],"break":[53],"dependency":[55],"between":[56],"PLD":[58,140],"dedicated":[60,71,153],"style.":[67],"Indeed,":[68],"PLDs":[70],"always":[76],"style-oriented.":[77],"innovative":[79],"aspects":[80],"described":[85],"in":[86,131,147],"details.":[87],"Moreover,":[88],"structure":[90,109],"well":[92],"suited":[93],"be":[95,114],"adapted":[96],"with":[97,116],"further":[98],"evolutions":[101],"thanks":[102],"genericity.":[106],"flexible":[111],"enough":[112],"used":[115],"different":[117,133],"design":[122],"flows.":[123],"As":[124],"an":[125],"example,":[126],"full-adder":[128],"was":[129],"implemented":[130],"two":[132],"demonstrate":[138],"flexibility.":[142],"included":[146],"larger":[149],"project":[150],"called":[151],"TAST,":[152],"synthesis":[156],"multistyle":[161]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}