{"id":"https://openalex.org/W2153575635","doi":"https://doi.org/10.1109/fpl.2005.1515702","title":"Using DSP blocks for ROM replacement: a novel synthesis flow","display_name":"Using DSP blocks for ROM replacement: a novel synthesis flow","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2153575635","doi":"https://doi.org/10.1109/fpl.2005.1515702","mag":"2153575635"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515702","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084087951","display_name":"Gareth W. Morris","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"G.W. Morris","raw_affiliation_strings":["Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College London, London, UK","Department of Electronic and Electrical Engineering, Circuits and Systems Group, London","Imperial College London, London, London, GB"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Circuits and Systems Group, London","institution_ids":[]},{"raw_affiliation_string":"Imperial College London, London, London, GB","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077866485","display_name":"G.A. Constantinides","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"G.A. Constantinides","raw_affiliation_strings":["Dept. of Electron. & Electr. Eng., Imperial Coll., London, UK"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Electr. Eng., Imperial Coll., London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"P.Y.K. Cheung","raw_affiliation_strings":["Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College London, London, UK","Department of Electronic and Electrical Engineering, Circuits and Systems Group, London"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Circuits and Systems Group, London","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5084087951"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":3.9911,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.93757509,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"19","issue":null,"first_page":"77","last_page":"82"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.9303480386734009},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7826688289642334},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7584569454193115},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6475494503974915},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6073852777481079},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5940403342247009},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5556845664978027},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.48593154549598694},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47837987542152405},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4542939066886902},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44920268654823303},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4479055106639862},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37316080927848816},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24828901886940002},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13196507096290588}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.9303480386734009},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7826688289642334},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7584569454193115},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6475494503974915},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6073852777481079},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5940403342247009},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5556845664978027},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.48593154549598694},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47837987542152405},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4542939066886902},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44920268654823303},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4479055106639862},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37316080927848816},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24828901886940002},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13196507096290588},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2005.1515702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515702","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.385.7426","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.7426","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cas.ee.ic.ac.uk/people/gac1/pubs/GarethFPL05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1600183590","https://openalex.org/W1767781815","https://openalex.org/W1787437284","https://openalex.org/W1977966390","https://openalex.org/W2058775467","https://openalex.org/W2127585914","https://openalex.org/W2144736151"],"related_works":["https://openalex.org/W2306407715","https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W3146054601","https://openalex.org/W2269990635","https://openalex.org/W2029518208","https://openalex.org/W4285464654","https://openalex.org/W3013057549","https://openalex.org/W2906427691","https://openalex.org/W2507786429"],"abstract_inverted_index":{"This":[0],"paper":[1,36],"describes":[2],"a":[3,61,75,131],"method":[4],"based":[5,100],"on":[6,38,67,82,101],"polynomial":[7],"approximation":[8],"for":[9,121,140],"transferring":[10],"ROM":[11],"resources":[12],"used":[13],"in":[14,60,78,92],"FPGA":[15,29],"designs":[16,65,139],"to":[17,27,94,104],"multiplication":[18],"and":[19,46,58,90,111,126],"addition":[20,93],"operations.":[21],"The":[22,50,70,97],"technique":[23],"can":[24],"be":[25],"applied":[26],"any":[28],"architecture":[30],"containing":[31],"embedded":[32],"multiplication,":[33],"however":[34],"this":[35],"focuses":[37],"using":[39],"the":[40,105,135,141,147,150],"DSP":[41,87],"blocks":[42],"of":[43,73,85,123,137,149],"Altera":[44,106],"Stratix":[45,47],"II":[48,108],"architectures.":[49],"transformation":[51],"is":[52,77,99,128],"combined":[53],"with":[54],"other":[55],"resource":[56],"transfers":[57],"integrated":[59],"synthesis":[62,109],"flow":[63,98],"targeting":[64],"implemented":[66],"heterogeneous":[68],"FPGAs.":[69],"main":[71],"advantage":[72],"such":[74],"system":[76],"handling":[79],"user":[80],"constraints":[81],"each":[83],"type":[84],"resource:":[86],"block,":[88],"LUT":[89],"ROM,":[91],"timing-related":[95],"constraints.":[96],"an":[102],"extension":[103],"Quartus":[107,112],"software":[110],"University":[113],"Interface":[114],"Program":[115],"(QUIP)":[116],"framework.":[117],"Results":[118],"are":[119],"provided":[120],"implementations":[122],"benchmark":[124],"algorithms":[125,142],"it":[127],"shown":[129],"through":[130],"design-space":[132],"exploration":[133],"that":[134],"set":[136],"achievable":[138],"has":[143],"been":[144],"extended":[145],"by":[146],"use":[148],"proposed":[151],"methods.":[152]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
