{"id":"https://openalex.org/W2109217033","doi":"https://doi.org/10.1109/fmcad.2009.5351123","title":"Industrial strength refinement checking","display_name":"Industrial strength refinement checking","publication_year":2009,"publication_date":"2009-11-01","ids":{"openalex":"https://openalex.org/W2109217033","doi":"https://doi.org/10.1109/fmcad.2009.5351123","mag":"2109217033"},"language":"en","primary_location":{"id":"doi:10.1109/fmcad.2009.5351123","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fmcad.2009.5351123","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Formal Methods in Computer-Aided Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067218159","display_name":"Jesse Bingham","orcid":"https://orcid.org/0000-0001-7015-0440"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Jesse Bingham","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102947598","display_name":"John Erickson","orcid":"https://orcid.org/0000-0003-3078-4566"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"John Erickson","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066646559","display_name":"Gaurav Singh","orcid":"https://orcid.org/0000-0002-8418-0154"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Gaurav Singh","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035272262","display_name":"Flemming Littrup Andersen","orcid":"https://orcid.org/0000-0003-2821-1849"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Flemming Andersen","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9033,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.71302958,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"180","last_page":"183"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8556563258171082},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.7070057988166809},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.6897533535957336},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6756429672241211},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6137290596961975},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.5634551048278809},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5043519735336304},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.43777069449424744},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.33577781915664673},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3250887393951416},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3248922824859619},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27503007650375366},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.23760873079299927},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.122304767370224},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.10904398560523987}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8556563258171082},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.7070057988166809},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.6897533535957336},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6756429672241211},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6137290596961975},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.5634551048278809},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5043519735336304},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.43777069449424744},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.33577781915664673},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3250887393951416},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3248922824859619},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27503007650375366},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.23760873079299927},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.122304767370224},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.10904398560523987}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fmcad.2009.5351123","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fmcad.2009.5351123","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Formal Methods in Computer-Aided Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.193.3051","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.193.3051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.ubc.ca/%7Ejbingham/short_fmcad2009.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1493919131","https://openalex.org/W1559982914","https://openalex.org/W1741528175","https://openalex.org/W1988520356","https://openalex.org/W2054198444","https://openalex.org/W2087702998","https://openalex.org/W2096700601","https://openalex.org/W2111422492","https://openalex.org/W2116989825","https://openalex.org/W2119341106","https://openalex.org/W2132107743","https://openalex.org/W2137182662","https://openalex.org/W2141772875","https://openalex.org/W2571737579","https://openalex.org/W6637675132","https://openalex.org/W6674917782","https://openalex.org/W6732077479"],"related_works":["https://openalex.org/W1539379314","https://openalex.org/W2462966030","https://openalex.org/W2037121848","https://openalex.org/W4312733571","https://openalex.org/W2006962382","https://openalex.org/W2149716943","https://openalex.org/W4315606162","https://openalex.org/W2340807904","https://openalex.org/W1547517160","https://openalex.org/W1483297389"],"abstract_inverted_index":{"This":[0],"paper":[1],"discusses":[2],"a":[3,23,42,54,57,87,95,148],"methodology":[4,96,106],"used":[5],"on":[6],"an":[7,80,155],"industrial":[8],"hardware":[9],"development":[10],"project":[11,150],"to":[12,21,37,67,72,144],"validate":[13],"various":[14],"cache-coherence":[15],"protocol":[16],"components.":[17],"The":[18],"idea":[19],"is":[20,83,107,122],"use":[22,38,139],"high":[24],"level":[25],"model":[26,32,120],"(HLM)":[27],"written":[28],"in":[29,147],"Murphi":[30,119],"for":[31,64,97],"checking":[33],"purposes,":[34],"and":[35,76,93,153],"then":[36],"the":[39,51,65,69,118,137],"HLM":[40],"as":[41],"checker":[43,55],"during":[44],"dynamic":[45],"(i.e.":[46],"simulation":[47,130],"based-)":[48],"validation":[49],"of":[50,60,104,140],"RTL.":[52],"Such":[53],"requires":[56],"formal":[58],"notion":[59,82,88],"what":[61],"it":[62],"means":[63],"RTL":[66,73],"implement":[68],"HLM.":[70],"Due":[71],"pipelining,":[74],"concurrency,":[75],"different":[77],"RTL/HLM":[78],"semantics,":[79],"appropriate":[81],"non-obvious.":[84],"We":[85,135],"employ":[86],"we":[89],"call":[90],"behavioral":[91],"refinement,":[92],"describe":[94],"creating":[98],"refinement":[99,142],"checkers.":[100],"A":[101],"novel":[102],"aspect":[103],"our":[105,141,158],"that":[108],"all":[109],"\u00bfingredients\u00bf":[110],"are":[111],"specified":[112],"using":[113],"System":[114],"Verilog":[115],"(SV):":[116],"even":[117],"itself":[121],"compiled":[123],"into":[124],"SV.":[125],"Thus":[126],"any":[127],"off-the-shelf":[128],"SV":[129],"engine":[131],"can":[132],"be":[133],"used.":[134],"report":[136],"successful":[138],"checkers":[143],"catch":[145],"bugs":[146],"real":[149],"at":[151],"Intel":[152],"give":[154],"example":[156],"illustrating":[157],"methodology.":[159]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}