{"id":"https://openalex.org/W4414433513","doi":"https://doi.org/10.1109/fdl68117.2025.11165408","title":"A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids","display_name":"A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids","publication_year":2025,"publication_date":"2025-09-10","ids":{"openalex":"https://openalex.org/W4414433513","doi":"https://doi.org/10.1109/fdl68117.2025.11165408"},"language":"en","primary_location":{"id":"doi:10.1109/fdl68117.2025.11165408","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fdl68117.2025.11165408","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Forum on Specification & Design Languages (FDL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5119704425","display_name":"Lars Luchterhandt","orcid":null},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Lars Luchterhandt","raw_affiliation_strings":["Paderborn University,Heinz Nixdorf Institute,Paderborn,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paderborn University,Heinz Nixdorf Institute,Paderborn,Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104080209","display_name":"Vivek Govindasamy","orcid":"https://orcid.org/0009-0005-4745-3669"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek Govindasamy","raw_affiliation_strings":["University of California,Center for Embedded and Cyber-Physical Systems,Irvine,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Center for Embedded and Cyber-Physical Systems,Irvine,CA,USA","institution_ids":["https://openalex.org/I204250578","https://openalex.org/I4210145666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100631529","display_name":"Yutong Wang","orcid":"https://orcid.org/0000-0002-8686-6598"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yutong Wang","raw_affiliation_strings":["University of California,Center for Embedded and Cyber-Physical Systems,Irvine,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Center for Embedded and Cyber-Physical Systems,Irvine,CA,USA","institution_ids":["https://openalex.org/I204250578","https://openalex.org/I4210145666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042898125","display_name":"J. Christoph Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christoph Scheytt","raw_affiliation_strings":["Paderborn University,Heinz Nixdorf Institute,Paderborn,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paderborn University,Heinz Nixdorf Institute,Paderborn,Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110622459","display_name":"Wolfgang M\u00fcller","orcid":"https://orcid.org/0000-0001-6474-3733"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Mueller","raw_affiliation_strings":["Paderborn University,Heinz Nixdorf Institute,Paderborn,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paderborn University,Heinz Nixdorf Institute,Paderborn,Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111950361","display_name":"Rainer D\u00f6mer","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rainer D\u00f6mer","raw_affiliation_strings":["University of California,Center for Embedded and Cyber-Physical Systems,Irvine,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Center for Embedded and Cyber-Physical Systems,Irvine,CA,USA","institution_ids":["https://openalex.org/I204250578","https://openalex.org/I4210145666"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5119704425"],"corresponding_institution_ids":["https://openalex.org/I206945453"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.26702969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.8059999942779541},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.629800021648407},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.6248000264167786},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.51910001039505},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4519999921321869},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4471000134944916},{"id":"https://openalex.org/keywords/software-design","display_name":"Software design","score":0.4465000033378601},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.43389999866485596}],"concepts":[{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.8059999942779541},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7581999897956848},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.629800021648407},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6248000264167786},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.51910001039505},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4519999921321869},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4471000134944916},{"id":"https://openalex.org/C52913732","wikidata":"https://www.wikidata.org/wiki/Q857102","display_name":"Software design","level":4,"score":0.4465000033378601},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.43389999866485596},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.3815999925136566},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.3718000054359436},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35929998755455017},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.35100001096725464},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33799999952316284},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3052999973297119},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.29159998893737793},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.2879999876022339},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.28540000319480896},{"id":"https://openalex.org/C76518257","wikidata":"https://www.wikidata.org/wiki/Q271680","display_name":"Software framework","level":5,"score":0.2849999964237213},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.2824999988079071},{"id":"https://openalex.org/C108215451","wikidata":"https://www.wikidata.org/wiki/Q7263963","display_name":"Simulation modeling","level":2,"score":0.2732999920845032},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26919999718666077},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2635999917984009},{"id":"https://openalex.org/C154488198","wikidata":"https://www.wikidata.org/wiki/Q1335007","display_name":"Embedded software","level":3,"score":0.26350000500679016},{"id":"https://openalex.org/C2777466363","wikidata":"https://www.wikidata.org/wiki/Q17008971","display_name":"Design tool","level":2,"score":0.2540999948978424},{"id":"https://openalex.org/C77405623","wikidata":"https://www.wikidata.org/wiki/Q598451","display_name":"System dynamics","level":2,"score":0.25119999051094055}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fdl68117.2025.11165408","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fdl68117.2025.11165408","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Forum on Specification & Design Languages (FDL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1498455513","https://openalex.org/W1983394510","https://openalex.org/W2076732255","https://openalex.org/W2080808587","https://openalex.org/W2094969361","https://openalex.org/W2122740326","https://openalex.org/W2172307690","https://openalex.org/W2531886805","https://openalex.org/W2693411020","https://openalex.org/W2913135501","https://openalex.org/W2967855397","https://openalex.org/W3027968530","https://openalex.org/W3035842346","https://openalex.org/W4240172596","https://openalex.org/W4241986871","https://openalex.org/W4243948044","https://openalex.org/W4249613718","https://openalex.org/W4254602193","https://openalex.org/W4384339318","https://openalex.org/W4401568405","https://openalex.org/W4405578731"],"related_works":[],"abstract_inverted_index":{"Even":[0],"when":[1],"following":[2],"a":[3,59,72,131],"well-structured":[4],"top-down":[5,60],"design":[6],"methodology,":[7],"system":[8,124],"designers":[9],"regularly":[10],"face":[11],"obstacles":[12],"and":[13,21,26,54,78,81,93,110],"pitfalls":[14],"posed":[15],"by":[16,41],"speed/accuracy":[17],"tradeoffs":[18,106],"in":[19,58,107],"modeling":[20,33],"simulation":[22,38,134],"of":[23,44,75],"complex":[24],"hardware":[25],"software":[27,69,133],"systems.":[28],"Across":[29],"the":[30,83,104,123],"abstraction":[31,87,101],"levels,":[32,88],"details":[34],"grow":[35],"exponentially,":[36],"while":[37],"speed":[39],"decreases":[40],"multiple":[42],"orders":[43],"magnitude.":[45],"To":[46],"quantify":[47],"these":[48],"effects,":[49],"we":[50],"systematically":[51],"generate,":[52],"simulate,":[53],"evaluate":[55],"grid-based":[56],"systems-on-chip":[57],"open-source":[61],"based":[62],"tool":[63],"flow.":[64],"We":[65],"map":[66],"two":[67],"parallel":[68],"applications":[70],"onto":[71],"scalable":[73],"grid":[74],"RISC-V":[76],"processors":[77],"successively":[79],"refine":[80],"validate":[82],"models":[84],"at":[85],"lower":[86],"namely":[89],"TLM,":[90],"ISS,":[91],"RTL,":[92],"FPGA.":[94],"Our":[95],"comprehensive":[96],"experimental":[97],"evaluation":[98],"over":[99],"five":[100],"levels":[102],"quantifies":[103],"speed-accuracy":[105],"simulator":[108],"build":[109],"run":[111],"times.":[112],"In":[113],"addition":[114],"to":[115,130],"its":[116],"educational":[117],"value,":[118],"our":[119],"work":[120],"can":[121],"guide":[122],"designer":[125],"on":[126,135],"an":[127],"efficient":[128],"path":[129],"cycle-accurate":[132],"fully":[136],"constructed":[137],"hardware.":[138]},"counts_by_year":[],"updated_date":"2026-04-29T09:16:38.111599","created_date":"2025-10-10T00:00:00"}