{"id":"https://openalex.org/W4387444442","doi":"https://doi.org/10.1109/fdl59689.2023.10272131","title":"Virtual Prototype Driven Application Specific Hardware Optimization","display_name":"Virtual Prototype Driven Application Specific Hardware Optimization","publication_year":2023,"publication_date":"2023-09-13","ids":{"openalex":"https://openalex.org/W4387444442","doi":"https://doi.org/10.1109/fdl59689.2023.10272131"},"language":"en","primary_location":{"id":"doi:10.1109/fdl59689.2023.10272131","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/fdl59689.2023.10272131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Forum on Specification &amp; Design Languages (FDL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068094095","display_name":"Jan Zielasko","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Jan Zielasko","raw_affiliation_strings":["DFKI GmbH,Cyber-Physical Systems,Bremen,Germany,28359"],"affiliations":[{"raw_affiliation_string":"DFKI GmbH,Cyber-Physical Systems,Bremen,Germany,28359","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["DFKI GmbH,Cyber-Physical Systems,Bremen,Germany,28359","DFKI GmbH,Cyber-Physical Systems,Bremen,Germany,28359; Institute of Computer Science, University of Bremen, Bremen, Germany"],"affiliations":[{"raw_affiliation_string":"DFKI GmbH,Cyber-Physical Systems,Bremen,Germany,28359","institution_ids":[]},{"raw_affiliation_string":"DFKI GmbH,Cyber-Physical Systems,Bremen,Germany,28359; Institute of Computer Science, University of Bremen, Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5068094095"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6181,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63630653,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.827617347240448},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6326997876167297},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.6156970262527466},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5275192856788635},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4673215448856354},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4575961232185364},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.42027217149734497},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3508272171020508},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3370741903781891},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32837358117103577},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.25742313265800476},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.14267495274543762}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.827617347240448},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6326997876167297},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.6156970262527466},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5275192856788635},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4673215448856354},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4575961232185364},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.42027217149734497},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3508272171020508},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3370741903781891},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32837358117103577},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.25742313265800476},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.14267495274543762},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fdl59689.2023.10272131","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/fdl59689.2023.10272131","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 Forum on Specification &amp; Design Languages (FDL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.4099999964237213}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321114","display_name":"Bundesministerium f\u00fcr Bildung und Forschung","ror":"https://ror.org/04pz7b180"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1978301594","https://openalex.org/W1989881690","https://openalex.org/W2187802606","https://openalex.org/W2624991222","https://openalex.org/W2791403216","https://openalex.org/W3005967710","https://openalex.org/W3040708363","https://openalex.org/W4212773764","https://openalex.org/W4220856780","https://openalex.org/W4229441435","https://openalex.org/W4243394032","https://openalex.org/W4312068755"],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W2160632767","https://openalex.org/W4241206086","https://openalex.org/W2109697164","https://openalex.org/W2543290882","https://openalex.org/W1528726807","https://openalex.org/W1964556228","https://openalex.org/W3047975009","https://openalex.org/W2156420848","https://openalex.org/W1905101075"],"abstract_inverted_index":{"Most":[0],"hardware":[1,24,46,115,138],"in":[2],"the":[3,18,23,66,73,94],"area":[4],"of":[5,96],"IoT":[6],"and":[7,20,34,40,98],"embedded":[8],"systems":[9],"only":[10],"ever":[11],"runs":[12],"a":[13,126,133],"single":[14],"application.":[15,30],"To":[16],"reduce":[17],"cost":[19],"increase":[21],"performance":[22],"can":[25,128],"be":[26,129],"tailored":[27],"to":[28,52,59,92,111],"this":[29,61],"Unfortunately,":[31],"identifying,":[32],"designing,":[33],"evaluating":[35],"application-specific":[36,45,137],"optimizations":[37],"is":[38],"complex":[39],"requires":[41],"significant":[42],"effort.":[43],"However,":[44],"also":[47],"performs":[48],"significantly":[49],"better":[50],"compared":[51],"using":[53],"general-purpose":[54],"processors.":[55],"Prior":[56],"work":[57],"attempts":[58],"address":[60],"problem":[62],"via":[63],"approaches":[64,84,100],"from":[65],"Register-Transfer":[67],"Level":[68],"(RTL)":[69],"as":[70,72,132],"well":[71],"application":[74],"level,":[75],"with":[76],"RTL":[77],"being":[78],"effective":[79],"but":[80,87],"resource-intensive,":[81],"while":[82],"high-level":[83,97],"are":[85],"faster":[86],"lack":[88],"accuracy.":[89],"In":[90],"order":[91],"combine":[93],"advantages":[95],"low-level":[99],"we":[101],"propose":[102],"an":[103],"open":[104],"source":[105],"Virtual":[106],"Prototype":[107],"(VP)":[108],"based":[109,118],"workflow":[110],"automatically":[112],"identify":[113],"promising":[114],"optimization":[116],"candidates":[117],"on":[119],"recurring":[120],"patterns.":[121],"Our":[122],"results":[123],"demonstrate":[124],"that":[125],"VP":[127],"used":[130],"effectively":[131],"starting":[134],"point":[135],"for":[136],"optimization.":[139]},"counts_by_year":[{"year":2024,"cited_by_count":2}],"updated_date":"2025-12-25T23:11:45.687758","created_date":"2025-10-10T00:00:00"}
