{"id":"https://openalex.org/W3095806684","doi":"https://doi.org/10.1109/fdl50818.2020.9232940","title":"A Minimal RISC-V Vector Processor for Embedded Systems","display_name":"A Minimal RISC-V Vector Processor for Embedded Systems","publication_year":2020,"publication_date":"2020-09-15","ids":{"openalex":"https://openalex.org/W3095806684","doi":"https://doi.org/10.1109/fdl50818.2020.9232940","mag":"3095806684"},"language":"en","primary_location":{"id":"doi:10.1109/fdl50818.2020.9232940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fdl50818.2020.9232940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Forum for Specification and Design Languages (FDL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108219478","display_name":"M. Johns","orcid":null},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Matthew Johns","raw_affiliation_strings":["School of Electronics and Computer Science, University of Southampton, Southampton, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics and Computer Science, University of Southampton, Southampton, United Kingdom","institution_ids":["https://openalex.org/I43439940"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040523899","display_name":"Tom J. K\u00e1zmierski","orcid":null},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Tom J. Kazmierski","raw_affiliation_strings":["School of Electronics and Computer Science, University of Southampton, Southampton, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics and Computer Science, University of Southampton, Southampton, United Kingdom","institution_ids":["https://openalex.org/I43439940"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108219478"],"corresponding_institution_ids":["https://openalex.org/I43439940"],"apc_list":null,"apc_paid":null,"fwci":4.0088,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.94570582,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.8525320291519165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7437413334846497},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.6340904831886292},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6076988577842712},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5055961608886719},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.4948121905326843},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.4932195544242859},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48578646779060364},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.44400885701179504},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4127890467643738}],"concepts":[{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.8525320291519165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7437413334846497},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.6340904831886292},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6076988577842712},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5055961608886719},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.4948121905326843},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.4932195544242859},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48578646779060364},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.44400885701179504},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4127890467643738}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fdl50818.2020.9232940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fdl50818.2020.9232940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 Forum for Specification and Design Languages (FDL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2040073568","https://openalex.org/W2078726412","https://openalex.org/W2551988222","https://openalex.org/W2613264175","https://openalex.org/W2782980666","https://openalex.org/W2994193159","https://openalex.org/W3123542955"],"related_works":["https://openalex.org/W2371982579","https://openalex.org/W2993622674","https://openalex.org/W2534569838","https://openalex.org/W4367172762","https://openalex.org/W182515070","https://openalex.org/W4364295250","https://openalex.org/W3116750762","https://openalex.org/W2164026451","https://openalex.org/W4310584696","https://openalex.org/W4226479694"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,14,23,79],"first":[4],"RISC-V":[5,16,25,87],"vector":[6,46],"processor":[7],"design":[8],"aimed":[9,31],"at":[10,32,60,97],"microcontrollers":[11],"that":[12],"uses":[13],"new":[15],"`V'":[17],"extension":[18],"for":[19,55,78,89],"vectors,":[20],"part":[21],"of":[22,41,96],"open-source":[24],"instruction":[26],"set":[27],"architecture":[28],"(ISA).":[29],"Being":[30],"small":[33],"embedded":[34],"devices,":[35],"it":[36],"demonstrates":[37],"a":[38,84],"simpler":[39],"method":[40],"parallel":[42],"execution":[43],"than":[44],"traditional":[45],"architectures":[47],"to":[48,76,83],"minimise":[49],"logic.":[50],"It":[51],"has":[52,71],"been":[53,66,72],"synthesised":[54],"testing":[56],"on":[57],"an":[58,90],"FPGA":[59,93],"50MHz.":[61],"Typical":[62],"vector-compatible":[63],"applications":[64,81],"have":[65],"used":[67],"as":[68],"benchmarks.":[69],"Performance":[70],"improved":[73],"by":[74],"up":[75],"5.8x":[77],"demonstrated":[80],"relative":[82],"comparable":[85],"scalar":[86],"processor,":[88],"increase":[91],"in":[92],"resource":[94],"utilisation":[95],"most":[98],"2.6x.":[99]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":11},{"year":2024,"cited_by_count":14},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":6}],"updated_date":"2026-05-10T08:33:47.465468","created_date":"2025-10-10T00:00:00"}