{"id":"https://openalex.org/W7164157265","doi":"https://doi.org/10.1109/fccm68464.2026.00055","title":"Design Space Exploration for Layer Pipelined DNN Accelerators Based on FPGAs","display_name":"Design Space Exploration for Layer Pipelined DNN Accelerators Based on FPGAs","publication_year":2026,"publication_date":"2026-05-13","ids":{"openalex":"https://openalex.org/W7164157265","doi":"https://doi.org/10.1109/fccm68464.2026.00055"},"language":null,"primary_location":{"id":"doi:10.1109/fccm68464.2026.00055","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm68464.2026.00055","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 34th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022920045","display_name":"Yiwei Wang","orcid":"https://orcid.org/0000-0002-1572-0989"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiwei Wang","raw_affiliation_strings":["Fudan University,School of Microelectronics,Shanghai,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,School of Microelectronics,Shanghai,China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5138349737","display_name":"Chang Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Wu","raw_affiliation_strings":["Fudan University,School of Microelectronics,Shanghai,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,School of Microelectronics,Shanghai,China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.94616507,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"267","last_page":"267"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.12349999696016312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.12349999696016312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.07540000230073929,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.07259999960660934,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.607699990272522},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.574400007724762},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5041999816894531},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.39239999651908875},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.3855000138282776},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.36880001425743103},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.33219999074935913}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.607699990272522},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5828999876976013},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.574400007724762},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5041999816894531},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42250001430511475},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.39239999651908875},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.3855000138282776},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.36880001425743103},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.33219999074935913},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.30570000410079956},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2971999943256378},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.2784000039100647},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2711000144481659},{"id":"https://openalex.org/C187107819","wikidata":"https://www.wikidata.org/wiki/Q835696","display_name":"NASA Deep Space Network","level":3,"score":0.2667999863624573},{"id":"https://openalex.org/C77304879","wikidata":"https://www.wikidata.org/wiki/Q211485","display_name":"Space technology","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.26420000195503235},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.2547000050544739},{"id":"https://openalex.org/C2778751112","wikidata":"https://www.wikidata.org/wiki/Q835016","display_name":"Window (computing)","level":2,"score":0.25189998745918274}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fccm68464.2026.00055","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm68464.2026.00055","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 34th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5705133676528931,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2996843284","https://openalex.org/W3164019007","https://openalex.org/W4402196566"],"related_works":[],"abstract_inverted_index":{"Design":[0],"space":[1],"exploration":[2],"(DSE)":[3],"aims":[4],"to":[5,94,132],"search":[6],"for":[7,12,29,49,67,85],"the":[8,96],"best":[9,97],"design":[10],"architecture":[11],"a":[13,18,26,53,73],"given":[14,68],"neural":[15],"network":[16],"on":[17,101],"target":[19],"device.":[20],"In":[21],"this":[22],"paper,":[23],"we":[24],"propose":[25],"DSE":[27,54,92],"engine":[28,93],"FPGAs,":[30],"considering":[31],"multi-core":[32],"layer-pipelined":[33],"designs.":[34],"Our":[35],"main":[36],"contributions":[37],"include":[38],"(1)":[39],"an":[40],"accurate":[41],"model":[42],"of":[43,58],"resource":[44,61],"usage":[45],"and":[46,62,71,82,103,137],"computation":[47,80],"throughput":[48,81],"pipeline":[50,86,108,124,129],"designs,":[51],"(2)":[52],"solver":[55],"with":[56,115],"consideration":[57],"both":[59],"on-chip":[60,138],"off-chip":[63,134],"memory":[64,135,139],"bandwidth":[65,136],"limitations":[66],"FPGA":[69],"boards":[70],"(3)":[72],"configurable":[74],"computing":[75],"core.":[76],"The":[77,118],"balance":[78],"between":[79],"data":[83],"transmission":[84],"designs":[87,109,125,130],"is":[88],"considered":[89],"in":[90],"our":[91,107],"achieve":[95,110],"performance.":[98],"Experimental":[99],"results":[100,119],"ResNet-18":[102],"VGG-16":[104],"demonstrate":[105],"that":[106,122],"1.17\u00d7\u20134.41\u00d7":[111],"performance":[112],"improvements":[113],"compared":[114],"state-of-the-art":[116],"baselines.":[117],"also":[120],"show":[121],"group-based":[123],"may":[126],"outperform":[127],"full":[128],"due":[131],"limited":[133],"resource.":[140]},"counts_by_year":[],"updated_date":"2026-06-12T06:20:11.936012","created_date":"2026-06-11T00:00:00"}
