{"id":"https://openalex.org/W3210272314","doi":"https://doi.org/10.1109/ewdts52692.2021.9581045","title":"Standard Cell Library Enhancement For Mixed Multi-Height Cell Design Implementation","display_name":"Standard Cell Library Enhancement For Mixed Multi-Height Cell Design Implementation","publication_year":2021,"publication_date":"2021-09-10","ids":{"openalex":"https://openalex.org/W3210272314","doi":"https://doi.org/10.1109/ewdts52692.2021.9581045","mag":"3210272314"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts52692.2021.9581045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts52692.2021.9581045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044210013","display_name":"Suren Abazyan","orcid":"https://orcid.org/0000-0002-1152-7938"},"institutions":[{"id":"https://openalex.org/I196551433","display_name":"Yerevan State University","ror":"https://ror.org/00s8vne50","country_code":"AM","type":"education","lineage":["https://openalex.org/I196551433"]}],"countries":["AM"],"is_corresponding":true,"raw_author_name":"Suren Abazyan","raw_affiliation_strings":["\u201cSynopsys Armenia\u201d CJSC, Yerevan State University, Yerevan, Armenia","\"Synopsys Armenia\" CJSC, Yerevan State University, Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"\u201cSynopsys Armenia\u201d CJSC, Yerevan State University, Yerevan, Armenia","institution_ids":["https://openalex.org/I196551433"]},{"raw_affiliation_string":"\"Synopsys Armenia\" CJSC, Yerevan State University, Yerevan, Armenia","institution_ids":["https://openalex.org/I196551433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5044210013"],"corresponding_institution_ids":["https://openalex.org/I196551433"],"apc_list":null,"apc_paid":null,"fwci":0.4063,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.6166373,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.8221768736839294},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.7039321660995483},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7016932964324951},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5009686946868896},{"id":"https://openalex.org/keywords/block-size","display_name":"Block size","score":0.4382944405078888},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32007119059562683},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3078576922416687},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2827815115451813},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22122561931610107},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.20751380920410156},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09656009078025818},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0805511474609375}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.8221768736839294},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.7039321660995483},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7016932964324951},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5009686946868896},{"id":"https://openalex.org/C41431624","wikidata":"https://www.wikidata.org/wiki/Q1053357","display_name":"Block size","level":3,"score":0.4382944405078888},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32007119059562683},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3078576922416687},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2827815115451813},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22122561931610107},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.20751380920410156},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09656009078025818},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0805511474609375},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts52692.2021.9581045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts52692.2021.9581045","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2000719225","https://openalex.org/W2039556638","https://openalex.org/W2090857935","https://openalex.org/W2738393560","https://openalex.org/W2941642691","https://openalex.org/W3136664717","https://openalex.org/W4233568622","https://openalex.org/W4251366091"],"related_works":["https://openalex.org/W2077189200","https://openalex.org/W2393136772","https://openalex.org/W768788828","https://openalex.org/W53339341","https://openalex.org/W4386229429","https://openalex.org/W3016449295","https://openalex.org/W2484416673","https://openalex.org/W2345938231","https://openalex.org/W2123931954","https://openalex.org/W4362564423"],"abstract_inverted_index":{"In":[0],"current":[1],"technologies,":[2],"standard":[3,122],"cell":[4,11,80,93,123,178],"libraries":[5,32,81],"are":[6,33],"being":[7],"designed":[8],"with":[9,98,118,149],"different":[10,91],"heights":[12],"for":[13,52,82],"performance,":[14],"area,":[15],"etc.":[16,71],"optimization.":[17],"For":[18],"better":[19],"trade-off":[20],"between":[21],"area":[22,95,125],"usage":[23,43,168],"and":[24,60,66,138,166],"performance":[25,140],"of":[26,31,55,102,113,162,175],"integrated":[27],"circuit,":[28],"these":[29],"types":[30],"mostly":[34],"used":[35],"together":[36],"in":[37,87,147],"one":[38,88],"design,":[39],"however":[40],"their":[41,84],"mixed":[42],"has":[44],"many":[45],"restrictions,":[46],"such":[47],"as":[48],"minimum":[49],"tile":[50],"selection":[51],"each":[53],"type":[54,101],"library,":[56],"separate":[57],"block":[58,89],"creation":[59],"integration":[61],"into":[62],"top":[63],"block,":[64],"power":[65,167],"ground":[67],"metal":[68],"grid":[69],"changes,":[70],"Proposed":[72],"method":[73],"is":[74,104,156,169],"using":[75,119],"special":[76,100],"approach":[77],"to":[78,106,133],"multi-height":[79],"increasing":[83],"cross-usage":[85],"capability":[86],"without":[90],"height":[92],"placement":[94,112],"separation.":[96],"Along":[97],"this,":[99],"cells":[103],"created":[105],"fill":[107],"empty":[108],"areas":[109],"after":[110],"successful":[111],"cells.":[114],"Experiments":[115],"show,":[116],"that":[117],"proposed":[120],"approach,":[121],"design":[124,137],"can":[126,141],"be":[127,142],"optimized":[128,143],"by":[129,144,158,171],"about":[130,145,159,172],"19,2%":[131],"compared":[132],"pure":[134,150],"12":[135],"track":[136,152],"timing":[139],"14.3%":[146],"comparison":[148],"9":[151],"design.":[153],"However,":[154],"runtime":[155],"increased":[157,170],"26.9%":[160],"because":[161,174],"physical":[163],"data":[164],"post-processing":[165],"12.8%,":[173],"big":[176],"drive":[177],"usage.":[179]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2}],"updated_date":"2026-04-02T15:55:50.835912","created_date":"2025-10-10T00:00:00"}
