{"id":"https://openalex.org/W3210905668","doi":"https://doi.org/10.1109/ewdts52692.2021.9580985","title":"Design and Verification of Novel Sync Cell","display_name":"Design and Verification of Novel Sync Cell","publication_year":2021,"publication_date":"2021-09-10","ids":{"openalex":"https://openalex.org/W3210905668","doi":"https://doi.org/10.1109/ewdts52692.2021.9580985","mag":"3210905668"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts52692.2021.9580985","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts52692.2021.9580985","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111904968","display_name":"Vazgen Melikyan","orcid":"https://orcid.org/0000-0002-1667-6860"},"institutions":[{"id":"https://openalex.org/I191043459","display_name":"National Polytechnic University of Armenia","ror":"https://ror.org/007b9cn27","country_code":"AM","type":"education","lineage":["https://openalex.org/I191043459"]}],"countries":["AM"],"is_corresponding":true,"raw_author_name":"Vazgen Melikyan","raw_affiliation_strings":["Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia","institution_ids":["https://openalex.org/I191043459"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112698731","display_name":"Stepan Harutyunyan","orcid":null},"institutions":[{"id":"https://openalex.org/I191043459","display_name":"National Polytechnic University of Armenia","ror":"https://ror.org/007b9cn27","country_code":"AM","type":"education","lineage":["https://openalex.org/I191043459"]}],"countries":["AM"],"is_corresponding":false,"raw_author_name":"Stepan Harutyunyan","raw_affiliation_strings":["Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia","institution_ids":["https://openalex.org/I191043459"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036349778","display_name":"Taron Kaplanyan","orcid":null},"institutions":[{"id":"https://openalex.org/I191043459","display_name":"National Polytechnic University of Armenia","ror":"https://ror.org/007b9cn27","country_code":"AM","type":"education","lineage":["https://openalex.org/I191043459"]}],"countries":["AM"],"is_corresponding":false,"raw_author_name":"Taron Kaplanyan","raw_affiliation_strings":["Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia","institution_ids":["https://openalex.org/I191043459"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079952489","display_name":"Artak Kirakosyan","orcid":null},"institutions":[{"id":"https://openalex.org/I153718931","display_name":"University of Ottawa","ror":"https://ror.org/03c4mmv16","country_code":"CA","type":"education","lineage":["https://openalex.org/I153718931"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Artak Kirakosyan","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Canada"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Canada","institution_ids":["https://openalex.org/I153718931"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085149734","display_name":"Arsen Momjyan","orcid":null},"institutions":[{"id":"https://openalex.org/I191043459","display_name":"National Polytechnic University of Armenia","ror":"https://ror.org/007b9cn27","country_code":"AM","type":"education","lineage":["https://openalex.org/I191043459"]}],"countries":["AM"],"is_corresponding":false,"raw_author_name":"Arsen Momjyan","raw_affiliation_strings":["Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia","institution_ids":["https://openalex.org/I191043459"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084222036","display_name":"Vardan Amiryan","orcid":null},"institutions":[{"id":"https://openalex.org/I191043459","display_name":"National Polytechnic University of Armenia","ror":"https://ror.org/007b9cn27","country_code":"AM","type":"education","lineage":["https://openalex.org/I191043459"]}],"countries":["AM"],"is_corresponding":false,"raw_author_name":"Vardan Amiryan","raw_affiliation_strings":["Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia"],"affiliations":[{"raw_affiliation_string":"Synopsys Armenia Educational Department, Chair of Microelectronic Circuits and Systems National Polytechnic, University of Armenia, Yerevan, Armenia","institution_ids":["https://openalex.org/I191043459"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5111904968"],"corresponding_institution_ids":["https://openalex.org/I191043459"],"apc_list":null,"apc_paid":null,"fwci":0.4606,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.60855159,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.915530800819397},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6869591474533081},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6361211538314819},{"id":"https://openalex.org/keywords/sync","display_name":"sync","score":0.5770683288574219},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5438088178634644},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5293726921081543},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.4336530566215515},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4137503206729889},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.41298437118530273},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.25105422735214233},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2487587034702301},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19286948442459106},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17246684432029724},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16079244017601013},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14216649532318115},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11476290225982666},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.10723385214805603},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09375271201133728},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0921194851398468},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.08569559454917908}],"concepts":[{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.915530800819397},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6869591474533081},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6361211538314819},{"id":"https://openalex.org/C3913047","wikidata":"https://www.wikidata.org/wiki/Q1956265","display_name":"sync","level":3,"score":0.5770683288574219},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5438088178634644},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5293726921081543},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.4336530566215515},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4137503206729889},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.41298437118530273},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.25105422735214233},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2487587034702301},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19286948442459106},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17246684432029724},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16079244017601013},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14216649532318115},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11476290225982666},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.10723385214805603},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09375271201133728},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0921194851398468},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.08569559454917908},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts52692.2021.9580985","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts52692.2021.9580985","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1544623790","https://openalex.org/W1550099581","https://openalex.org/W1965019509","https://openalex.org/W1974317131","https://openalex.org/W2066746455","https://openalex.org/W2103681490","https://openalex.org/W2187779671","https://openalex.org/W3147673367","https://openalex.org/W4240233328"],"related_works":["https://openalex.org/W4312550058","https://openalex.org/W4386998367","https://openalex.org/W786632520","https://openalex.org/W1983405009","https://openalex.org/W60393894","https://openalex.org/W2095703739","https://openalex.org/W2378481815","https://openalex.org/W2110629111","https://openalex.org/W2349909378","https://openalex.org/W794031490"],"abstract_inverted_index":{"A":[0],"novel":[1],"approach":[2,14,38],"of":[3,31,70,103,112],"clock":[4,105],"domain":[5],"crossing":[6],"solution":[7],"is":[8,56],"presented.":[9],"For":[10,107],"high-frequency":[11,34,63,125],"conditions":[12],"traditional":[13,82,92],"calls":[15],"for":[16,19,48,74,81],"multiple":[17],"D-flops":[18],"single":[20],"bit":[21],"synchronization.":[22,76],"The":[23,151],"higher":[24,28,143],"the":[25,27,29,45,67,94,108,116,144,147],"frequency":[26],"number":[30],"flops.":[32],"In":[33],"solutions,":[35],"such":[36],"an":[37],"can":[39,59],"consume":[40],"much-needed":[41],"space":[42],"and":[43,85],"limit":[44],"useful":[46],"area":[47,69],"additional":[49,99,104],"logic.":[50],"Hence":[51],"a":[52,113],"new":[53],"mixed-signal":[54],"circuit":[55,96],"introduced":[57],"which":[58],"be":[60],"used":[61,73],"in":[62,101,124],"applications":[64],"to":[65],"reduce":[66],"overall":[68],"synchronizer":[71],"logic":[72],"single-bit":[75],"Comparison":[77],"has":[78,97,119],"been":[79],"done":[80],"multi-flop":[83],"synchronization":[84,131],"proposed":[86,95,117],"design":[87,118],"with":[88,155],"analog":[89],"comparators.":[90],"Unlike":[91],"design,":[93],"no":[98],"delays":[100],"form":[102],"cycles.":[106],"usual":[109],"use":[110],"case":[111],"two-stage":[114],"synchronizer,":[115],"20%":[120],"more":[121,130,148],"area,":[122],"but":[123],"applications,":[126],"where":[127],"three":[128],"or":[129],"stages":[132],"are":[133,138],"used,":[134],"at":[135],"least":[136],"30%":[137],"reduction":[139,149],"was":[140,153],"achieved":[141],"(the":[142],"stage":[145],"number,":[146],"percentage).":[150],"simulation":[152],"performed":[154],"SAED":[156],"32/28":[157],"nm":[158],"technology.":[159]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
