{"id":"https://openalex.org/W3093893536","doi":"https://doi.org/10.1109/ewdts50664.2020.9225129","title":"Hardware Implementation of Timed Logical Control FSM","display_name":"Hardware Implementation of Timed Logical Control FSM","publication_year":2020,"publication_date":"2020-09-01","ids":{"openalex":"https://openalex.org/W3093893536","doi":"https://doi.org/10.1109/ewdts50664.2020.9225129","mag":"3093893536"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts50664.2020.9225129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts50664.2020.9225129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112331777","display_name":"Maryna Miroschnyk","orcid":null},"institutions":[{"id":"https://openalex.org/I4210151026","display_name":"Ukrainian State University of Railway Transport","ror":"https://ror.org/05f8ce979","country_code":"UA","type":"education","lineage":["https://openalex.org/I4210151026"]}],"countries":["UA"],"is_corresponding":true,"raw_author_name":"Maryna Miroschnyk","raw_affiliation_strings":["USURT, Kharkiv, Ukraine"],"affiliations":[{"raw_affiliation_string":"USURT, Kharkiv, Ukraine","institution_ids":["https://openalex.org/I4210151026"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017713857","display_name":"Alexander Shkil","orcid":"https://orcid.org/0000-0003-1071-3445"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alexander Shkil","raw_affiliation_strings":["KhNURE, Kharkiv, Ukraine"],"affiliations":[{"raw_affiliation_string":"KhNURE, Kharkiv, Ukraine","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029071876","display_name":"\u0414\u0430\u0440\u0456\u044f \u0420\u0430\u0445\u043b\u0456\u0441","orcid":"https://orcid.org/0000-0002-6652-1840"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dariia Rakhlis","raw_affiliation_strings":["KhNURE, Kharkiv, Ukraine"],"affiliations":[{"raw_affiliation_string":"KhNURE, Kharkiv, Ukraine","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056169678","display_name":"Elvira Kulak","orcid":"https://orcid.org/0000-0002-8441-5187"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Elvira Kulak","raw_affiliation_strings":["KhNURE, Kharkiv, Ukraine"],"affiliations":[{"raw_affiliation_string":"KhNURE, Kharkiv, Ukraine","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008981399","display_name":"Inna Filippenko","orcid":"https://orcid.org/0000-0002-3584-2107"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Inna Filippenko","raw_affiliation_strings":["KhNURE, Kharkiv, Ukraine"],"affiliations":[{"raw_affiliation_string":"KhNURE, Kharkiv, Ukraine","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069854768","display_name":"Mykyta Malakhov","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mykyta Malakhov","raw_affiliation_strings":["KhNURE, Kharkiv, Ukraine"],"affiliations":[{"raw_affiliation_string":"KhNURE, Kharkiv, Ukraine","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5112331777"],"corresponding_institution_ids":["https://openalex.org/I4210151026"],"apc_list":null,"apc_paid":null,"fwci":0.2814,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63087502,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"51","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8655462861061096},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8244823217391968},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.7687783241271973},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.7229669094085693},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7156552076339722},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.700935959815979},{"id":"https://openalex.org/keywords/timed-automaton","display_name":"Timed automaton","score":0.4682551324367523},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4601185619831085},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4454089105129242},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36352068185806274},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2740134000778198},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.16758951544761658}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8655462861061096},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8244823217391968},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.7687783241271973},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.7229669094085693},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7156552076339722},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.700935959815979},{"id":"https://openalex.org/C30788636","wikidata":"https://www.wikidata.org/wiki/Q7805517","display_name":"Timed automaton","level":3,"score":0.4682551324367523},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4601185619831085},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4454089105129242},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36352068185806274},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2740134000778198},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.16758951544761658}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts50664.2020.9225129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts50664.2020.9225129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W635506153","https://openalex.org/W2017501663","https://openalex.org/W2101508170","https://openalex.org/W2110970068","https://openalex.org/W2570047840","https://openalex.org/W2783548027","https://openalex.org/W2884238308","https://openalex.org/W2954234184","https://openalex.org/W3084260542","https://openalex.org/W3161410102","https://openalex.org/W4244927124"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W146887057","https://openalex.org/W1917852300","https://openalex.org/W2391435730","https://openalex.org/W2384838054","https://openalex.org/W1750171350","https://openalex.org/W2139058049","https://openalex.org/W2381282135","https://openalex.org/W2724597727","https://openalex.org/W2508541108"],"abstract_inverted_index":{"Methods":[0],"of":[1,4,15,26,39,52,70,75],"hardware":[2,64],"implementation":[3,80,88],"event-driven":[5],"timed":[6,16],"control":[7,17],"FSM":[8,18,57],"were":[9,43,94],"considered":[10],"in":[11,61,67,81],"the":[12,24,37,50,62,68],"article.":[13],"Classification":[14],"into":[19,31],"active":[20],"and":[21,30,33,79],"passive":[22],"by":[23,36,49],"method":[25,38],"processing":[27],"input":[28],"signals,":[29],"Moore":[32],"Mealy":[34],"models":[35,58],"generating":[40],"output":[41],"signals":[42],"given.":[44],"Timing":[45],"parameters":[46],"are":[47,59],"implemented":[48],"counter":[51],"FSM'":[53],"clock":[54],"cycles.":[55],"Timed":[56],"presented":[60],"VHDL":[63],"description":[65],"language":[66],"form":[69],"automata":[71],"pattern.":[72],"Behavioral":[73],"simulation":[74,86],"proposed":[76],"models,":[77],"synthesis":[78],"FPGA,":[82],"as":[83,85],"well":[84],"after":[87],"using":[89],"CAD":[90],"Xilinx":[91],"ISE":[92],"14.7":[93],"performed.":[95]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}