{"id":"https://openalex.org/W2770031882","doi":"https://doi.org/10.1109/ewdts.2017.8110092","title":"Application of exhaustive search, branch and bound, parallel computing and Monte-Carlo methods for the synthesis of quasi-optimal network-on-chip topologies","display_name":"Application of exhaustive search, branch and bound, parallel computing and Monte-Carlo methods for the synthesis of quasi-optimal network-on-chip topologies","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2770031882","doi":"https://doi.org/10.1109/ewdts.2017.8110092","mag":"2770031882"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2017.8110092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2017.8110092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060261504","display_name":"A. Yu. Romanov","orcid":"https://orcid.org/0000-0002-9410-9431"},"institutions":[{"id":"https://openalex.org/I118501908","display_name":"National Research University Higher School of Economics","ror":"https://ror.org/055f7t516","country_code":"RU","type":"education","lineage":["https://openalex.org/I118501908"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"Aleksandr Romanov","raw_affiliation_strings":["National Research University, Higher School of Economics, Moscow, Russian Federation"],"affiliations":[{"raw_affiliation_string":"National Research University, Higher School of Economics, Moscow, Russian Federation","institution_ids":["https://openalex.org/I118501908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042822390","display_name":"I. I. Romanova","orcid":"https://orcid.org/0000-0002-2047-4225"},"institutions":[{"id":"https://openalex.org/I118501908","display_name":"National Research University Higher School of Economics","ror":"https://ror.org/055f7t516","country_code":"RU","type":"education","lineage":["https://openalex.org/I118501908"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Irina Romanova","raw_affiliation_strings":["National Research University, Higher School of Economics, Moscow, Russian Federation"],"affiliations":[{"raw_affiliation_string":"National Research University, Higher School of Economics, Moscow, Russian Federation","institution_ids":["https://openalex.org/I118501908"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084715176","display_name":"Alexander Ivannikov","orcid":"https://orcid.org/0000-0001-8162-5288"},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I1313323035","https://openalex.org/I4210096404","https://openalex.org/I4210097085"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Alexander Ivannikov","raw_affiliation_strings":["The Institute for Design Problems in Microelectronics of Russian Academy of Sciences, Moscow, Russian Federation"],"affiliations":[{"raw_affiliation_string":"The Institute for Design Problems in Microelectronics of Russian Academy of Sciences, Moscow, Russian Federation","institution_ids":["https://openalex.org/I4210096404"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5060261504"],"corresponding_institution_ids":["https://openalex.org/I118501908"],"apc_list":null,"apc_paid":null,"fwci":0.4144,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.67407361,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9772999882698059,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9743000268936157,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.917971670627594},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6435596942901611},{"id":"https://openalex.org/keywords/adjacency-matrix","display_name":"Adjacency matrix","score":0.6369678974151611},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5499290823936462},{"id":"https://openalex.org/keywords/adjacency-list","display_name":"Adjacency list","score":0.45073947310447693},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4400838315486908},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4250171184539795},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38344311714172363},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37062886357307434},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2527334988117218},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.22765323519706726},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.07261133193969727},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06772544980049133}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.917971670627594},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6435596942901611},{"id":"https://openalex.org/C180356752","wikidata":"https://www.wikidata.org/wiki/Q727035","display_name":"Adjacency matrix","level":3,"score":0.6369678974151611},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5499290823936462},{"id":"https://openalex.org/C110484373","wikidata":"https://www.wikidata.org/wiki/Q264398","display_name":"Adjacency list","level":2,"score":0.45073947310447693},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4400838315486908},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4250171184539795},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38344311714172363},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37062886357307434},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2527334988117218},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.22765323519706726},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.07261133193969727},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06772544980049133},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2017.8110092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2017.8110092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1503001724","https://openalex.org/W1548168045","https://openalex.org/W1920261463","https://openalex.org/W2003856929","https://openalex.org/W2081787664","https://openalex.org/W2140029418","https://openalex.org/W2147632348","https://openalex.org/W2156790537","https://openalex.org/W2560916850","https://openalex.org/W3020882730","https://openalex.org/W4238520168","https://openalex.org/W6640131421"],"related_works":["https://openalex.org/W4213150077","https://openalex.org/W2369410163","https://openalex.org/W2059018062","https://openalex.org/W2604585036","https://openalex.org/W2078477160","https://openalex.org/W1989103179","https://openalex.org/W1991172810","https://openalex.org/W125803343","https://openalex.org/W2117632582","https://openalex.org/W4388347373"],"abstract_inverted_index":{"On":[0],"the":[1,15,39,70,77,90,98,112],"basis":[2],"of":[3,41,92,100,114],"an":[4],"integrated":[5],"network-on-chip":[6],"(NoC)":[7],"topologies":[8,84,110],"optimality":[9],"criterion,":[10],"as":[11,13],"well":[12],"applying":[14],"adjacency":[16],"matrix":[17],"to":[18,38,62,72,102,117],"describe":[19],"NoC":[20,42],"topologies,":[21],"exhaustive":[22],"search":[23],"method":[24,91],"and":[25,31,33,76,108],"its":[26],"modification":[27],"by":[28,88],"using":[29,89],"branch":[30],"bound":[32],"Monte-Carlo":[34],"methods":[35],"are":[36],"extended":[37],"synthesis":[40,49,85,101],"quasi-optimal":[43,64],"topologies.":[44],"Designed":[45],"ScaNoC":[46],"suboptimal":[47],"topology":[48],"algorithm":[50,86],"is":[51],"implemented":[52],"on":[53],"a":[54],"high-level":[55],"programming":[56],"language":[57],"which":[58],"makes":[59],"it":[60],"possible":[61],"generate":[63],"topological":[65],"solutions":[66],"in":[67],"accordance":[68],"with":[69,111],"requirements":[71],"reduce":[73],"hardware":[74],"costs":[75],"average":[78],"distance":[79],"between":[80],"nodes.":[81],"Proposed":[82],"quasioptimal":[83],"improvement":[87],"parallel":[93],"computing":[94],"allows":[95],"speeding":[96],"up":[97,116],"process":[99],"2":[103],"<sup":[104],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[105],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">117</sup>":[106],"times":[107],"getting":[109],"number":[113],"nodes":[115],"18.":[118]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
