{"id":"https://openalex.org/W2569620432","doi":"https://doi.org/10.1109/ewdts.2016.7807719","title":"An improved scheme for pre-computed patterns in core-based SoC architecture","display_name":"An improved scheme for pre-computed patterns in core-based SoC architecture","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2569620432","doi":"https://doi.org/10.1109/ewdts.2016.7807719","mag":"2569620432"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2016.7807719","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807719","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["arxiv","crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/1711.08975","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014717235","display_name":"Elaheh Sadredini","orcid":"https://orcid.org/0000-0002-5834-4346"},"institutions":[{"id":"https://openalex.org/I67009956","display_name":"Iran University of Science and Technology","ror":"https://ror.org/01jw2p796","country_code":"IR","type":"education","lineage":["https://openalex.org/I67009956"]},{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Elaheh Sadredini","raw_affiliation_strings":["Computer Enflineering Department, Iran University of Science and Technology, Iran","Electrical and Computer Engineering Department, University of Tehran, Iran","Computer Engineering Department Iran University of Science and Technology, Iran"],"affiliations":[{"raw_affiliation_string":"Computer Enflineering Department, Iran University of Science and Technology, Iran","institution_ids":["https://openalex.org/I67009956"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Computer Engineering Department Iran University of Science and Technology, Iran","institution_ids":["https://openalex.org/I67009956"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020409722","display_name":"Reza Rahimi","orcid":null},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Reza Rahimi","raw_affiliation_strings":["Computer Engineering Department, Sharif University of Technology, Iran"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Department, Sharif University of Technology, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054234277","display_name":"Paniz Foroutan","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Paniz Foroutan","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Tehran, Iran","Electricai and Computer Engineering Department, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Electricai and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056796328","display_name":"Mahmood Fathy","orcid":"https://orcid.org/0000-0003-0852-5488"},"institutions":[{"id":"https://openalex.org/I67009956","display_name":"Iran University of Science and Technology","ror":"https://ror.org/01jw2p796","country_code":"IR","type":"education","lineage":["https://openalex.org/I67009956"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mahmood Fathy","raw_affiliation_strings":["Computer Enflineering Department, Iran University of Science and Technology, Iran","Computer Engineering Department Iran University of Science and Technology, Iran"],"affiliations":[{"raw_affiliation_string":"Computer Enflineering Department, Iran University of Science and Technology, Iran","institution_ids":["https://openalex.org/I67009956"]},{"raw_affiliation_string":"Computer Engineering Department Iran University of Science and Technology, Iran","institution_ids":["https://openalex.org/I67009956"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Tehran, Iran","Electricai and Computer Engineering Department, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Electricai and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5014717235"],"corresponding_institution_ids":["https://openalex.org/I23946033","https://openalex.org/I67009956"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16180932,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7732663750648499},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6807283759117126},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.6058177351951599},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5922594666481018},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5418347716331482},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5327916741371155},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5246800780296326},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5222190618515015},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5159245729446411},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5122649073600769},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4583666920661926},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4516056776046753},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.447567343711853},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43198126554489136},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.42700278759002686},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42045992612838745},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38076481223106384},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15804508328437805},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15625622868537903},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.1428738236427307},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08306059241294861},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07256710529327393},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06446045637130737}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7732663750648499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6807283759117126},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.6058177351951599},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5922594666481018},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5418347716331482},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5327916741371155},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5246800780296326},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5222190618515015},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5159245729446411},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5122649073600769},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4583666920661926},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4516056776046753},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.447567343711853},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43198126554489136},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.42700278759002686},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42045992612838745},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38076481223106384},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15804508328437805},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15625622868537903},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.1428738236427307},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08306059241294861},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07256710529327393},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06446045637130737},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/ewdts.2016.7807719","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807719","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:1711.08975","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1711.08975","pdf_url":"https://arxiv.org/pdf/1711.08975","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"mag:2569620432","is_oa":true,"landing_page_url":"https://arxiv.org/pdf/1711.08975","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"arXiv (Cornell University)","raw_type":null},{"id":"doi:10.48550/arxiv.1711.08975","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.1711.08975","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:1711.08975","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1711.08975","pdf_url":"https://arxiv.org/pdf/1711.08975","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2569620432.pdf","grobid_xml":"https://content.openalex.org/works/W2569620432.grobid-xml"},"referenced_works_count":26,"referenced_works":["https://openalex.org/W1971520701","https://openalex.org/W1999000076","https://openalex.org/W2003295533","https://openalex.org/W2003299974","https://openalex.org/W2010806198","https://openalex.org/W2011989862","https://openalex.org/W2016217616","https://openalex.org/W2068937842","https://openalex.org/W2085780923","https://openalex.org/W2085955574","https://openalex.org/W2106186395","https://openalex.org/W2118597853","https://openalex.org/W2130725517","https://openalex.org/W2134369540","https://openalex.org/W2141744188","https://openalex.org/W2145675266","https://openalex.org/W2156546262","https://openalex.org/W2168875709","https://openalex.org/W2259014528","https://openalex.org/W2300780924","https://openalex.org/W2381967304","https://openalex.org/W3148473232","https://openalex.org/W4247367638","https://openalex.org/W4247382390","https://openalex.org/W4251664938","https://openalex.org/W6658376275"],"related_works":["https://openalex.org/W2137475190","https://openalex.org/W2551759005","https://openalex.org/W2587095215","https://openalex.org/W2133456190","https://openalex.org/W2118375748","https://openalex.org/W2185778875","https://openalex.org/W3086070586","https://openalex.org/W1562661222","https://openalex.org/W630529707","https://openalex.org/W2493193322","https://openalex.org/W2745332085","https://openalex.org/W1978748630","https://openalex.org/W2147563109","https://openalex.org/W2140900006","https://openalex.org/W2104122235","https://openalex.org/W2119175806","https://openalex.org/W2134930853","https://openalex.org/W2775012885","https://openalex.org/W2171716031","https://openalex.org/W3173558872"],"abstract_inverted_index":{"By":[0],"advances":[1],"in":[2,15,28,40,63,81,114],"technology,":[3],"integrated":[4],"circuits":[5,44,111],"have":[6,23],"come":[7],"to":[8],"include":[9],"more":[10,13,61],"functionality":[11],"and":[12,48,95],"complexity":[14,29],"a":[16,34],"single":[17],"chip.":[18,85],"Although":[19],"methods":[20],"of":[21,30,42,91,117],"testing":[22,33,41],"improved,":[24],"but":[25],"the":[26,50,89,97,115],"increase":[27],"circuits,":[31],"keeps":[32],"challenging":[35],"problem.":[36],"Two":[37],"important":[38,62],"challenges":[39,58],"digital":[43],"are":[45],"test":[46,53,79,93,99,118],"time":[47,101],"accessing":[49],"circuit":[51],"under":[52],"(CUT)":[54],"for":[55,76],"testing.":[56],"These":[57],"become":[59],"even":[60],"complex":[64],"system":[65],"on":[66,84,108],"chip":[67],"(SoC)":[68],"zone.":[69],"This":[70,86],"paper":[71],"presents":[72],"an":[73],"improved":[74],"scheme":[75],"generating":[77],"pre-computed":[78,92],"patterns":[80,94],"core-based":[82],"systems":[83],"approach":[87],"reduces":[88],"number":[90,116],"as":[96],"result,":[98],"application":[100],"(TAT)":[102],"will":[103],"be":[104],"decreased.":[105],"Experimental":[106],"results":[107],"ISCAS'89":[109],"benchmark":[110],"show":[112],"improvement":[113],"clock":[119],"cycles.":[120]},"counts_by_year":[],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}