{"id":"https://openalex.org/W2570013717","doi":"https://doi.org/10.1109/ewdts.2016.7807700","title":"A trace signal selection algorithm for improved post-silicon debug","display_name":"A trace signal selection algorithm for improved post-silicon debug","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2570013717","doi":"https://doi.org/10.1109/ewdts.2016.7807700","mag":"2570013717"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2016.7807700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807700","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100712187","display_name":"B\u0131nod Kumar","orcid":"https://orcid.org/0000-0002-6172-7938"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Binod Kumar","raw_affiliation_strings":["Computer Architecture and Dependable Systems Lab (CADSL), Indian Institute of Technology Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable Systems Lab (CADSL), Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045895620","display_name":"Ankit Jindal","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ankit Jindal","raw_affiliation_strings":["Computer Architecture and Dependable Systems Lab (CADSL), Indian Institute of Technology Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable Systems Lab (CADSL), Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Computer Architecture and Dependable Systems Lab (CADSL), Indian Institute of Technology Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable Systems Lab (CADSL), Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.4482,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.55701668,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.9547353982925415},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.8189817667007446},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8069937825202942},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.8055996894836426},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8052881956100464},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.6541569828987122},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.48945820331573486},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.4775867462158203},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43876782059669495},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4318389892578125},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3711090683937073},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1508251428604126},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11677801609039307}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.9547353982925415},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.8189817667007446},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8069937825202942},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.8055996894836426},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8052881956100464},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.6541569828987122},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.48945820331573486},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.4775867462158203},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43876782059669495},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4318389892578125},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3711090683937073},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1508251428604126},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11677801609039307},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2016.7807700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807700","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1981868262","https://openalex.org/W2014071060","https://openalex.org/W2024436253","https://openalex.org/W2042191662","https://openalex.org/W2090692734","https://openalex.org/W2122146819","https://openalex.org/W2153440685","https://openalex.org/W2159381165"],"related_works":["https://openalex.org/W2361273971","https://openalex.org/W2351581202","https://openalex.org/W2978026406","https://openalex.org/W2385068581","https://openalex.org/W2381166695","https://openalex.org/W4241045879","https://openalex.org/W2366346238","https://openalex.org/W2366922255","https://openalex.org/W2387706296","https://openalex.org/W2347893649"],"abstract_inverted_index":{"Enhancing":[0],"observability":[1],"is":[2,29,87],"a":[3,39],"key":[4],"challenge":[5],"in":[6,59],"post-silicon":[7],"validation.":[8],"On-chip":[9],"trace":[10,43,91],"buffers":[11],"store":[12],"real":[13],"time":[14],"data":[15,96],"which":[16,57,93],"can":[17],"be":[18],"used":[19],"for":[20,31,41,65,89],"analyzing":[21],"and":[22],"debugging.":[23,66],"Appropriate":[24],"selection":[25],"of":[26,50,53,62,75],"these":[27],"signals":[28,44,92],"crucial":[30],"storing":[32],"useful":[33,88],"debug":[34,76,95],"data.":[35,77],"This":[36],"paper":[37],"proposes":[38],"methodology":[40,86],"identifying":[42],"so":[45],"as":[46],"to":[47,72],"maximize":[48,94],"detection":[49],"erroneous":[51],"behavior":[52],"the":[54,85],"failing":[55],"chip":[56],"helps":[58],"improving":[60],"quality":[61],"information":[63],"available":[64],"Different":[67],"quantitative":[68],"measures":[69],"are":[70],"proposed":[71],"assess":[73],"utility":[74],"Experimental":[78],"results":[79],"on":[80],"benchmark":[81],"circuits":[82],"indicate":[83],"that":[84],"selecting":[90],"effectiveness.":[97]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
