{"id":"https://openalex.org/W2567902313","doi":"https://doi.org/10.1109/ewdts.2016.7807664","title":"Multiversion parallel synthesis of digital structures based on SystemC specification","display_name":"Multiversion parallel synthesis of digital structures based on SystemC specification","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2567902313","doi":"https://doi.org/10.1109/ewdts.2016.7807664","mag":"2567902313"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2016.7807664","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807664","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Vladimir Obrizan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vladimir Obrizan","raw_affiliation_strings":["KhNURE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KhNURE","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081892135","display_name":"Tetiana Soklakova","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tetiana Soklakova","raw_affiliation_strings":["KhNURE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KhNURE","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9732153415679932},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8130370378494263},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5042954683303833},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.48004448413848877},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4618624150753021},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4597601592540741},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.45703402161598206},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.10150983929634094},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08233946561813354}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9732153415679932},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8130370378494263},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5042954683303833},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.48004448413848877},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4618624150753021},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4597601592540741},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.45703402161598206},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.10150983929634094},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08233946561813354},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2016.7807664","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807664","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1533697147","https://openalex.org/W1905081946","https://openalex.org/W1993517433","https://openalex.org/W2068110570","https://openalex.org/W2117297857","https://openalex.org/W2141130413","https://openalex.org/W2223533251","https://openalex.org/W2540478631","https://openalex.org/W6677646588"],"related_works":["https://openalex.org/W2752828786","https://openalex.org/W2242433395","https://openalex.org/W2544073398","https://openalex.org/W2548514518","https://openalex.org/W2579932084","https://openalex.org/W1831349210","https://openalex.org/W2802530065","https://openalex.org/W1550409889","https://openalex.org/W1830510111","https://openalex.org/W2106574988"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,19,43],"multivesion":[4],"parallel":[5,58],"synthesis":[6,35,59],"of":[7,16,30,37,54,62],"digital":[8,31,39],"structures":[9],"based":[10,41],"on":[11,42],"SystemC":[12,47],"specification.":[13],"The":[14],"purpose":[15],"which":[17],"is":[18],"substantial":[20],"reduction":[21],"in":[22,46,66],"design":[23],"time":[24],"computing":[25],"architectures":[26],"and":[27,51,60],"increasing":[28],"quality":[29],"products":[32,40],"through":[33],"multiversion":[34],"structure":[36],"the":[38],"predetermined":[44],"specification":[45],"environments":[48],"(C":[49],"++)":[50],"automatic":[52],"selection":[53],"functional":[55],"components":[56],"by":[57],"verification":[61],"system-level":[63],"architectural":[64],"decisions":[65],"accordance":[67],"with":[68],"proposed":[69],"metric.":[70]},"counts_by_year":[],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}
