{"id":"https://openalex.org/W2570689982","doi":"https://doi.org/10.1109/ewdts.2016.7807650","title":"Multi-interval static timing analysis accounting logic compatibility","display_name":"Multi-interval static timing analysis accounting logic compatibility","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2570689982","doi":"https://doi.org/10.1109/ewdts.2016.7807650","mag":"2570689982"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2016.7807650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053906683","display_name":"S. V. Gavrilov","orcid":"https://orcid.org/0000-0003-0566-4482"},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Sergey Gavrilov","raw_affiliation_strings":["Russian Academy of Science, Institute for Design Problems in Microelectronics, Moscow, Zelenograd, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Russian Academy of Science, Institute for Design Problems in Microelectronics, Moscow, Zelenograd, Russia","institution_ids":["https://openalex.org/I4210096404"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031811599","display_name":"G.A. Ivanova","orcid":null},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Galina Ivanova","raw_affiliation_strings":["Russian Academy of Science, Institute for Design Problems in Microelectronics, Moscow, Zelenograd, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Russian Academy of Science, Institute for Design Problems in Microelectronics, Moscow, Zelenograd, Russia","institution_ids":["https://openalex.org/I4210096404"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061270530","display_name":"Daria Ryzhova","orcid":"https://orcid.org/0000-0002-7155-1892"},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Daria Ryzhova","raw_affiliation_strings":["Russian Academy of Science, Institute for Design Problems in Microelectronics, Moscow, Zelenograd, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Russian Academy of Science, Institute for Design Problems in Microelectronics, Moscow, Zelenograd, Russia","institution_ids":["https://openalex.org/I4210096404"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030879388","display_name":"Pavel Volobuev","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109776","display_name":"Research and Production Complex Technological Centre","ror":"https://ror.org/01pq8wx80","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210109776"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Pavel Volobuev","raw_affiliation_strings":["SMC \u201cTechnological Centre\u201d, Moscow, Zelenograd, Russia","SMC \"Technological Centre\", Moscow, Zelenograd, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SMC \u201cTechnological Centre\u201d, Moscow, Zelenograd, Russia","institution_ids":["https://openalex.org/I4210109776"]},{"raw_affiliation_string":"SMC \"Technological Centre\", Moscow, Zelenograd, Russia","institution_ids":["https://openalex.org/I4210109776"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.15325502,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":"2016","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7021045684814453},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.6693519353866577},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.595623254776001},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5819839239120483},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5103296637535095},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.49091607332229614},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4904343783855438},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4839039742946625},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45535045862197876},{"id":"https://openalex.org/keywords/interval","display_name":"Interval (graph theory)","score":0.4515655040740967},{"id":"https://openalex.org/keywords/interval-arithmetic","display_name":"Interval arithmetic","score":0.429067462682724},{"id":"https://openalex.org/keywords/variance","display_name":"Variance (accounting)","score":0.4231989085674286},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.41206660866737366},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4119926691055298},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.356235146522522},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.3347914218902588},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2784855365753174},{"id":"https://openalex.org/keywords/accounting","display_name":"Accounting","score":0.20102843642234802},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13955020904541016},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1223737895488739}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7021045684814453},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.6693519353866577},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.595623254776001},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5819839239120483},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5103296637535095},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.49091607332229614},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4904343783855438},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4839039742946625},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45535045862197876},{"id":"https://openalex.org/C2778067643","wikidata":"https://www.wikidata.org/wiki/Q166507","display_name":"Interval (graph theory)","level":2,"score":0.4515655040740967},{"id":"https://openalex.org/C191252586","wikidata":"https://www.wikidata.org/wiki/Q1671453","display_name":"Interval arithmetic","level":3,"score":0.429067462682724},{"id":"https://openalex.org/C196083921","wikidata":"https://www.wikidata.org/wiki/Q7915758","display_name":"Variance (accounting)","level":2,"score":0.4231989085674286},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.41206660866737366},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4119926691055298},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.356235146522522},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.3347914218902588},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2784855365753174},{"id":"https://openalex.org/C121955636","wikidata":"https://www.wikidata.org/wiki/Q4116214","display_name":"Accounting","level":1,"score":0.20102843642234802},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13955020904541016},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1223737895488739},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ewdts.2016.7807650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},{"id":"mag:2783790033","is_oa":false,"landing_page_url":"http://jglobal.jst.go.jp/en/public/20090422/201702256160640474","pdf_url":null,"source":{"id":"https://openalex.org/S4306512817","display_name":"IEEE Conference Proceedings","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"IEEE Conference Proceedings","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1605463408","https://openalex.org/W1990937339","https://openalex.org/W2016233710","https://openalex.org/W2018817743","https://openalex.org/W2065183790","https://openalex.org/W2080267935","https://openalex.org/W2107261135","https://openalex.org/W2115296652","https://openalex.org/W2170949280","https://openalex.org/W3144534410","https://openalex.org/W6666921160","https://openalex.org/W6676237635"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W3015599398","https://openalex.org/W2034656493","https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W2110367374","https://openalex.org/W3151506308","https://openalex.org/W1986294008","https://openalex.org/W2345182073","https://openalex.org/W1947426333"],"abstract_inverted_index":{"The":[0],"influence":[1],"of":[2,45,54],"technological":[3,62],"and":[4,63],"circuit":[5,11,64],"parameters":[6,66],"variations":[7],"on":[8,75,83],"the":[9,16,24,34,41,52,55,79,84,92,94],"combinational":[10],"elements":[12],"delay":[13,36,108],"increases":[14],"with":[15,51,88,110],"transistor":[17],"size":[18],"reduction.":[19],"Delay":[20],"uncertainty":[21,67],"comes":[22],"from":[23],"parameter":[25],"values":[26],"dispersion;":[27],"therefore,":[28],"it":[29,101],"is":[30,73],"critical":[31],"to":[32,43,60],"analyze":[33],"possible":[35],"variance.":[37],"This":[38],"paper":[39],"presents":[40],"solution":[42],"problems":[44],"complex":[46],"digital":[47],"circuits":[48],"performance":[49],"analysis":[50,81,109],"presence":[53],"aforementioned":[56],"uncertainty.":[57],"In":[58],"order":[59],"account":[61],"element":[65],"we":[68],"propose":[69],"a":[70],"method":[71,96],"which":[72],"based":[74,82],"interval":[76,107],"modeling.":[77],"Unlike":[78],"traditional":[80],"test":[85],"sequence":[86],"modeling":[87],"ordering":[89],"events":[90],"during":[91],"time,":[93],"proposed":[95],"provides":[97],"space":[98],"ordering,":[99],"thus":[100],"offers":[102],"significant":[103],"accuracy":[104],"increase":[105],"for":[106],"simultaneous":[111],"input":[112],"switching":[113],"consideration.":[114]},"counts_by_year":[{"year":2020,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
