{"id":"https://openalex.org/W2568853367","doi":"https://doi.org/10.1109/ewdts.2016.7807648","title":"Enabling LOS delay test with slow scan enable","display_name":"Enabling LOS delay test with slow scan enable","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2568853367","doi":"https://doi.org/10.1109/ewdts.2016.7807648","mag":"2568853367"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2016.7807648","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078604240","display_name":"Satyadev Ahlawat","orcid":"https://orcid.org/0000-0003-0186-1446"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Satyadev Ahlawat","raw_affiliation_strings":["Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010761729","display_name":"Darshit Vaghani","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Darshit Vaghani","raw_affiliation_strings":["Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018402972","display_name":"Rohini Gulve","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rohini Gulve","raw_affiliation_strings":["Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5078604240"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15911228,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.7285178899765015},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.7080057859420776},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6885068416595459},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6649417877197266},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.6096973419189453},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5998141169548035},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5124569535255432},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.48724690079689026},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.4843774735927582},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4800244867801666},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.4697219431400299},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.44279274344444275},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.4381049573421478},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39909762144088745},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37170594930648804},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2208789885044098},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2177976369857788},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19540300965309143},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.17360374331474304},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15968966484069824},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11737653613090515},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11087474226951599}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.7285178899765015},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.7080057859420776},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6885068416595459},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6649417877197266},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.6096973419189453},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5998141169548035},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5124569535255432},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.48724690079689026},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.4843774735927582},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4800244867801666},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.4697219431400299},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.44279274344444275},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.4381049573421478},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39909762144088745},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37170594930648804},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2208789885044098},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2177976369857788},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19540300965309143},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.17360374331474304},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15968966484069824},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11737653613090515},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11087474226951599},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2016.7807648","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2016.7807648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1908034516","https://openalex.org/W2106884550","https://openalex.org/W2112705672","https://openalex.org/W2116874325","https://openalex.org/W2167255265","https://openalex.org/W2533392450","https://openalex.org/W2762065359","https://openalex.org/W4240724929","https://openalex.org/W6676710984","https://openalex.org/W6677113358","https://openalex.org/W6684812068","https://openalex.org/W6745091166"],"related_works":["https://openalex.org/W2888456858","https://openalex.org/W2098411556","https://openalex.org/W2127184179","https://openalex.org/W2125077617","https://openalex.org/W1991667530","https://openalex.org/W2159919870","https://openalex.org/W2131198212","https://openalex.org/W2117137640","https://openalex.org/W1519664134","https://openalex.org/W2166638143"],"abstract_inverted_index":{"Delay":[0],"defects":[1],"can":[2,107,133],"be":[3,134],"detected":[4],"using":[5],"Launch-off-capture":[6],"(LOC)":[7],"and":[8,21,93,118],"Launch-off-shift":[9],"(LOS)":[10],"based":[11,73,95],"delay":[12,18,74,96,111],"test":[13,19,22,36,97,127],"techniques.":[14],"In":[15,59,76],"terms":[16],"of":[17,47,62,89],"coverage":[20,113],"set":[23],"size,":[24],"LOS":[25,35,92,117],"is":[26,43,56,87],"more":[27],"effective":[28],"compared":[29],"to":[30,33],"LOC.":[31],"However,":[32],"exercise":[34],"a":[37,49,81,99,123,138,145],"high":[38,50],"speed":[39,51],"scan":[40,53,68,83,101,126,131,140,148],"enable":[41,54,102],"signal":[42,55],"required.":[44],"The":[45,104],"cost":[46],"implementing":[48],"global":[52],"prohibitively":[57],"high.":[58],"practice,":[60],"most":[61],"the":[63,129],"commercial":[64],"designs":[65],"employing":[66],"full":[67],"design":[69,85,106],"support":[70],"only":[71],"LOC":[72,94,119],"test.":[75,120],"this":[77],"paper,":[78],"we":[79],"propose":[80],"new":[82],"flip-flop":[84,132],"that":[86],"capable":[88],"exercising":[90,115],"both":[91,116,136],"with":[98],"slow":[100],"signal.":[103],"proposed":[105,130],"achieve":[108],"much":[109],"higher":[110],"fault":[112],"by":[114],"Furthermore,":[121],"in":[122],"mixed":[124],"mode":[125],"environment":[128],"used":[135],"as":[137,142,144],"serial":[139],"cell":[141],"well":[143],"random":[146],"access":[147],"(RAS)":[149],"cell.":[150]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}