{"id":"https://openalex.org/W2444511150","doi":"https://doi.org/10.1109/ewdts.2015.7493153","title":"Process variation-aware approximation for efficient timing management of digital circuits","display_name":"Process variation-aware approximation for efficient timing management of digital circuits","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2444511150","doi":"https://doi.org/10.1109/ewdts.2015.7493153","mag":"2444511150"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2015.7493153","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2015.7493153","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083510197","display_name":"Mohsen Faryabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Mohsen Faryabi","raw_affiliation_strings":["College of Engineering, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085421646","display_name":"H. Dorosti","orcid":"https://orcid.org/0000-0001-6554-1607"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Hamed Dorosti","raw_affiliation_strings":["College of Engineering, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080817569","display_name":"Mehdi Modarressi","orcid":"https://orcid.org/0000-0002-4117-7609"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mehdi Modarressi","raw_affiliation_strings":["College of Engineering, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109197901","display_name":"Sied Mehdi Fakhraie","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Sied Mehdi Fakhraie","raw_affiliation_strings":["College of Engineering, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5083510197"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.20826693,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"57","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.8098006248474121},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.7100588083267212},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.669157087802887},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.608673095703125},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5885295867919922},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5838161110877991},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5801713466644287},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5630046725273132},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5243259072303772},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5227887034416199},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5174134969711304},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4846406579017639},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45357266068458557},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.44217681884765625},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4274284839630127},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38468030095100403},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.3382391333580017},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18677622079849243},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1354556381702423},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.123634934425354},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09169337153434753}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.8098006248474121},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.7100588083267212},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.669157087802887},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.608673095703125},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5885295867919922},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5838161110877991},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5801713466644287},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5630046725273132},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5243259072303772},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5227887034416199},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5174134969711304},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4846406579017639},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45357266068458557},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.44217681884765625},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4274284839630127},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38468030095100403},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.3382391333580017},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18677622079849243},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1354556381702423},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.123634934425354},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09169337153434753},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2015.7493153","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2015.7493153","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2005865544","https://openalex.org/W2017521824","https://openalex.org/W2020217519","https://openalex.org/W2045294186","https://openalex.org/W2076536455","https://openalex.org/W2110329567","https://openalex.org/W2119299853","https://openalex.org/W2135089667","https://openalex.org/W2135100177","https://openalex.org/W2143283746","https://openalex.org/W2150283124","https://openalex.org/W2166773037","https://openalex.org/W2170039577","https://openalex.org/W2187230075","https://openalex.org/W3139678091","https://openalex.org/W3147234326","https://openalex.org/W4234974086","https://openalex.org/W4240237526","https://openalex.org/W6680326947"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W3015599398","https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W2110367374","https://openalex.org/W3151506308","https://openalex.org/W1804063983","https://openalex.org/W1986294008","https://openalex.org/W2134944363","https://openalex.org/W2345182073"],"abstract_inverted_index":{"With":[0],"the":[1,24,35,41,64,71,115,118,134],"ever":[2],"decreasing":[3],"transistor":[4],"feature":[5],"size":[6,36],"in":[7,17,30,34,47,51,75,99],"recent":[8],"years,":[9],"process":[10,72,102],"variation":[11,33,73,127],"has":[12],"become":[13],"a":[14,91,148],"serious":[15],"challenge":[16],"digital":[18],"system":[19],"design,":[20],"mainly":[21],"due":[22],"to":[23,62,69,95,108,114,122],"undesirable":[25],"timing":[26,97],"uncertainty":[27],"it":[28],"introduces":[29],"circuits.":[31],"This":[32],"of":[37,101],"circuit":[38],"components":[39],"changes":[40],"logic":[42],"and":[43,164],"wire":[44],"delays":[45],"that":[46,126,143],"turn,":[48],"may":[49],"result":[50],"delay":[52,132,153],"faults":[53],"or":[54],"clock":[55],"degradation.":[56],"In":[57,79],"this":[58,80,144],"paper,":[59],"we":[60],"propose":[61],"use":[63],"emerging":[65],"approximate":[66,93],"computing":[67],"technique":[68],"tackle":[70],"problem":[74],"new":[76],"technology":[77],"points.":[78],"method,":[81],"functional":[82],"units":[83],"(sub-blocks)":[84],"along":[85],"critical":[86,109,123,135],"paths":[87,116],"are":[88],"replaced":[89],"with":[90,117],"faster":[92],"version":[94],"guarantee":[96],"closure":[98],"presence":[100],"variation.":[103],"Approximation":[104],"not":[105],"only":[106],"applies":[107],"path":[110,124],"sub-blocks":[111],"but":[112],"also":[113],"length":[119,125],"close":[120],"enough":[121],"can":[128,146],"potentially":[129],"increase":[130],"their":[131],"over":[133],"path.":[136],"Evaluation":[137],"results":[138],"under":[139],"several":[140],"benchmarks":[141],"show":[142],"method":[145],"give":[147],"required":[149],"safety":[150],"margin":[151],"against":[152],"faults,":[154],"while":[155],"its":[156],"side-effect,":[157],"i.e.":[158],"accuracy":[159],"loss,":[160],"is":[161],"still":[162],"low":[163],"acceptable.":[165]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
