{"id":"https://openalex.org/W2425689357","doi":"https://doi.org/10.1109/ewdts.2015.7493152","title":"Test program generation for mixed-signal integrated circuits based on automata network","display_name":"Test program generation for mixed-signal integrated circuits based on automata network","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2425689357","doi":"https://doi.org/10.1109/ewdts.2015.7493152","mag":"2425689357"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2015.7493152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2015.7493152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019089975","display_name":"Sergey Mosin","orcid":"https://orcid.org/0000-0003-1389-2602"},"institutions":[{"id":"https://openalex.org/I4210109043","display_name":"Vladimir State University","ror":"https://ror.org/01nxjpd08","country_code":"RU","type":"education","lineage":["https://openalex.org/I4210109043"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"Sergey Mosin","raw_affiliation_strings":["Computer engineering department, Vladimir State University (VSU), Vladimir, Russia"],"affiliations":[{"raw_affiliation_string":"Computer engineering department, Vladimir State University (VSU), Vladimir, Russia","institution_ids":["https://openalex.org/I4210109043"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5019089975"],"corresponding_institution_ids":["https://openalex.org/I4210109043"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.20041453,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.8320853114128113},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.703761637210846},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.6149221062660217},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5714013576507568},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.5292686223983765},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.45085495710372925},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.4402572810649872},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.4376688301563263},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42591696977615356},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.23412999510765076},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15551906824111938},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.14808496832847595},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.14480248093605042},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13131779432296753},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11118999123573303},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07274407148361206}],"concepts":[{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.8320853114128113},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.703761637210846},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.6149221062660217},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5714013576507568},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.5292686223983765},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.45085495710372925},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.4402572810649872},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.4376688301563263},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42591696977615356},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.23412999510765076},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15551906824111938},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.14808496832847595},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.14480248093605042},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13131779432296753},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11118999123573303},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07274407148361206},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2015.7493152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2015.7493152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE East-West Design &amp; Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1585191422","https://openalex.org/W1878994937","https://openalex.org/W1893675745","https://openalex.org/W1969278872","https://openalex.org/W2051631586","https://openalex.org/W2138223697","https://openalex.org/W2217346147","https://openalex.org/W6688807974"],"related_works":["https://openalex.org/W2031235560","https://openalex.org/W2062239751","https://openalex.org/W2113725540","https://openalex.org/W2035101737","https://openalex.org/W1846623049","https://openalex.org/W1863819993","https://openalex.org/W2161335888","https://openalex.org/W128516171","https://openalex.org/W2135509339","https://openalex.org/W2114773158"],"abstract_inverted_index":{"Testing":[0],"and":[1,10,23,26,88,92],"diagnosis":[2],"of":[3,33,47,60,70,86,96,103,131],"mixed-signal":[4,48,65,104,118,137],"integrated":[5],"circuits":[6],"are":[7,56,139],"very":[8],"important":[9],"complex":[11],"tasks,":[12],"which":[13],"require":[14],"selection":[15],"the":[16,37,44,52,68,76,84,109,112,126,132,136],"most":[17],"relevant":[18],"test":[19,45,61,79,90,98,114],"methods":[20,99],"for":[21,30,42,64,100,117,135],"analog":[22],"digital":[24],"subcircuits":[25],"subsequent":[27],"their":[28],"matching":[29,95],"comprehensive":[31],"testing":[32,102,120],"a":[34],"circuit":[35,138],"on":[36,51],"whole.":[38],"Two":[39],"basic":[40],"models":[41],"description":[43],"process":[46],"IC":[49,66,119],"based":[50],"algebraic":[53],"automata":[54,71],"theory":[55],"proposed.":[57],"The":[58,106],"method":[59,107,133],"program":[62,115],"generation":[63,116],"in":[67,75],"form":[69],"network":[72],"is":[73],"presented":[74],"paper.":[77],"Generated":[78],"programs":[80],"take":[81],"into":[82],"account":[83],"features":[85],"CUT":[87],"used":[89],"equipment":[91],"also":[93],"ensure":[94],"applied":[97],"hierarchical":[101],"IC.":[105],"provides":[108],"feasibility":[110],"to":[111],"automated":[113],"with":[121],"various":[122],"resolving":[123],"ability":[124],"using":[125],"state-of-the-art":[127],"ATE.":[128],"Experimental":[129],"results":[130],"application":[134],"presented.":[140]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
