{"id":"https://openalex.org/W1972475500","doi":"https://doi.org/10.1109/ewdts.2014.7027095","title":"Squaring in reversible logic using iterative structure","display_name":"Squaring in reversible logic using iterative structure","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W1972475500","doi":"https://doi.org/10.1109/ewdts.2014.7027095","mag":"1972475500"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2014.7027095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2014.7027095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014459472","display_name":"Arindam Banerjee","orcid":"https://orcid.org/0000-0002-7856-5699"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Arindam Banerjee","raw_affiliation_strings":["Dept. of CSE, Jadavpur University, Kolkata, India","Department of CSE, Jadavpur University, Kolkata-32, India"],"affiliations":[{"raw_affiliation_string":"Dept. of CSE, Jadavpur University, Kolkata, India","institution_ids":["https://openalex.org/I170979836"]},{"raw_affiliation_string":"Department of CSE, Jadavpur University, Kolkata-32, India","institution_ids":["https://openalex.org/I170979836"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059700720","display_name":"Debesh K. Das","orcid":"https://orcid.org/0000-0003-1736-1497"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Debesh Kumar Das","raw_affiliation_strings":["Dept. of CSE, Jadavpur University, Kolkata, India","Department of CSE, Jadavpur University, Kolkata-32, India"],"affiliations":[{"raw_affiliation_string":"Dept. of CSE, Jadavpur University, Kolkata, India","institution_ids":["https://openalex.org/I170979836"]},{"raw_affiliation_string":"Department of CSE, Jadavpur University, Kolkata-32, India","institution_ids":["https://openalex.org/I170979836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5014459472"],"corresponding_institution_ids":["https://openalex.org/I170979836"],"apc_list":null,"apc_paid":null,"fwci":0.409,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.72371562,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7230883836746216},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6035807132720947},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5884464383125305},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5838685035705566},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.51729416847229},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5086877942085266},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.49598726630210876},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.49322599172592163},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4892115592956543},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.47522619366645813},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4691801369190216},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4675622880458832},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41292381286621094},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3941299021244049},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3847714960575104},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3381778597831726},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2772432565689087},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17919012904167175},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.0996372401714325},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.09382578730583191}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7230883836746216},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6035807132720947},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5884464383125305},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5838685035705566},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.51729416847229},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5086877942085266},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.49598726630210876},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.49322599172592163},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4892115592956543},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.47522619366645813},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4691801369190216},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4675622880458832},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41292381286621094},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3941299021244049},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3847714960575104},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3381778597831726},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2772432565689087},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17919012904167175},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0996372401714325},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.09382578730583191},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2014.7027095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2014.7027095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6800000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1629802966","https://openalex.org/W1982891200","https://openalex.org/W2019042649","https://openalex.org/W2087890368","https://openalex.org/W2094122506"],"related_works":["https://openalex.org/W142017057","https://openalex.org/W2386022279","https://openalex.org/W2363153189","https://openalex.org/W4372324531","https://openalex.org/W1592424226","https://openalex.org/W2243536805","https://openalex.org/W659242671","https://openalex.org/W2356140560","https://openalex.org/W2370649629","https://openalex.org/W2152365648"],"abstract_inverted_index":{"Digital":[0,5],"multipliers":[1,48],"are":[2,17,135],"indispensable":[3],"in":[4,25,47,78,129],"signal":[6],"processing":[7],"and":[8,15,66,118,121,139],"cryptography.":[9],"In":[10],"many":[11,43],"mathematical":[12],"computations,":[13],"squaring":[14,32,76],"cubing":[16],"frequently":[18],"used.":[19],"Generally":[20],"the":[21,29,34,40,51,56,83,103,125,133],"multiplier":[22],"is":[23,94],"used":[24,46],"computing":[26],"square.":[27],"But":[28],"implementation":[30],"of":[31,42,74,113],"has":[33],"advantage":[35],"that":[36],"we":[37],"can":[38,140],"avoid":[39],"generation":[41],"partial":[44],"products":[45],"by":[49,97],"eliminating":[50],"redundant":[52],"bits,":[53],"thus":[54],"resulting":[55],"circuit":[57],"to":[58,85],"be":[59,141],"simpler":[60],"with":[61,102,124],"less":[62],"hardware,":[63],"propagation":[64],"delay":[65],"power":[67],"consumption.":[68],"Our":[69,108],"work":[70,127],"proposes":[71],"two":[72],"designs":[73,134],"dedicated":[75],"techniques":[77,109],"reversible":[79],"circuits.":[80],"We":[81],"use":[82,112],"recursion":[84],"achieve":[86],"our":[87],"design.":[88],"The":[89],"design":[90,104],"for":[91,105],"n":[92],"bits":[93],"recursively":[95],"obtained":[96],"appending":[98],"some":[99],"extra":[100],"circuitry":[101],"(n-1)":[106],"bits.":[107],"make":[110],"optimum":[111],"ancillary":[114],"inputs,":[115],"garbage":[116],"outputs":[117],"quantum":[119],"cost":[120],"compare":[122],"favourably":[123],"recent":[126],"[1]":[128],"this":[130],"area.":[131],"Both":[132],"having":[136],"modular":[137],"structures":[138],"systemically":[142],"designed.":[143]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}