{"id":"https://openalex.org/W2056533553","doi":"https://doi.org/10.1109/ewdts.2014.7027087","title":"Temperature aware test scheduling by modified floorplanning","display_name":"Temperature aware test scheduling by modified floorplanning","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2056533553","doi":"https://doi.org/10.1109/ewdts.2014.7027087","mag":"2056533553"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2014.7027087","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2014.7027087","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design &amp; Test Symposium (EWDTS 2014)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016275118","display_name":"Rawat Indira","orcid":null},"institutions":[{"id":"https://openalex.org/I56287899","display_name":"Maharshi Dayanand Saraswati University","ror":"https://ror.org/0229k3q35","country_code":"IN","type":"education","lineage":["https://openalex.org/I56287899"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Indira Rawat","raw_affiliation_strings":["Department of Electrical Engineering, Govt. Engineering College, Ajmer Rajasthan, India","Department of Electrical Engineering, Govt., Engineering College, Ajmer, Rajasthan, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Govt. Engineering College, Ajmer Rajasthan, India","institution_ids":["https://openalex.org/I56287899"]},{"raw_affiliation_string":"Department of Electrical Engineering, Govt., Engineering College, Ajmer, Rajasthan, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016031007","display_name":"Manish Gupta","orcid":"https://orcid.org/0000-0002-9702-0133"},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M.K. Gupta","raw_affiliation_strings":["Deptt. Of Electronics and Communication Engg., Maulana Azad National Institute of Technology, Bhopal, India","Deptt. Of Electronics and Communication Engg., Maulana Azad National, Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Deptt. Of Electronics and Communication Engg., Maulana Azad National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]},{"raw_affiliation_string":"Deptt. Of Electronics and Communication Engg., Maulana Azad National, Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Deptt. Of Electrical Engineering, Indian Institute of Technology, Mumbai, India"],"affiliations":[{"raw_affiliation_string":"Deptt. Of Electrical Engineering, Indian Institute of Technology, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5016275118"],"corresponding_institution_ids":["https://openalex.org/I56287899"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11752705,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9629334211349487},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6995202898979187},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5369681119918823},{"id":"https://openalex.org/keywords/stacking","display_name":"Stacking","score":0.48267582058906555},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4738341271877289},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4470962882041931},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3883083462715149},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.37339842319488525},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33023595809936523},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2963586449623108},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25313928723335266},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21780282258987427},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10453271865844727},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0880555510520935}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9629334211349487},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6995202898979187},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5369681119918823},{"id":"https://openalex.org/C33347731","wikidata":"https://www.wikidata.org/wiki/Q285210","display_name":"Stacking","level":2,"score":0.48267582058906555},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4738341271877289},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4470962882041931},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3883083462715149},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.37339842319488525},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33023595809936523},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2963586449623108},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25313928723335266},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21780282258987427},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10453271865844727},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0880555510520935},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2014.7027087","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2014.7027087","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design &amp; Test Symposium (EWDTS 2014)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1930934741","https://openalex.org/W2035224686","https://openalex.org/W2109556313","https://openalex.org/W2110090002","https://openalex.org/W2113126942","https://openalex.org/W2123406615","https://openalex.org/W2129130212","https://openalex.org/W2129960401","https://openalex.org/W2133863299","https://openalex.org/W2154857344","https://openalex.org/W4250768564","https://openalex.org/W4253995697","https://openalex.org/W6677118561"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W1500063550","https://openalex.org/W215057456","https://openalex.org/W2135118255","https://openalex.org/W2165891825","https://openalex.org/W2106366463","https://openalex.org/W1535718467","https://openalex.org/W4231092740","https://openalex.org/W1974421757","https://openalex.org/W4239364405"],"abstract_inverted_index":{"The":[0,118],"semiconductor":[1],"industry":[2],"is":[3,29,37,64],"always":[4],"looking":[5],"for":[6,149],"some":[7],"new":[8],"technology":[9],"in":[10,20,68,79,92,141],"order":[11],"to":[12,56,86,108,154],"house":[13],"the":[14,32,41,100,110,115,139],"ever":[15],"increasing":[16],"number":[17],"of":[18,40,99,112,127],"devices":[19],"as":[21,24,71,145,147],"small":[22],"area":[23],"possible.":[25],"One":[26],"such":[27],"solution":[28],"offered":[30],"by":[31],"three":[33],"dimensional":[34],"SoCs":[35],"which":[36,54],"vertical":[38],"stacking":[39],"various":[42,50,130],"dies.":[43],"It":[44,135],"also":[45,65],"has":[46,122,132],"associated":[47],"with":[48],"it":[49],"challenges":[51],"and":[52,73,125],"constraints":[53],"need":[55],"be":[57,87,144],"overcome":[58],"before":[59],"its":[60],"adoption.":[61],"Power":[62],"density":[63],"increasing,":[66],"resuling":[67],"increased":[69],"heat":[70,94],"more":[72,74,93],"functions":[75],"are":[76],"being":[77],"realised":[78],"a":[80,150],"single":[81],"chip.":[82,101],"Cooling":[83],"methods":[84],"have":[85,106],"adopted.":[88],"Again":[89],"testing":[90],"results":[91],"generation":[95],"than":[96],"functional":[97],"mode":[98],"In":[102],"this":[103],"paper":[104],"we":[105],"tried":[107],"analyze":[109],"effect":[111],"floorplanning":[113],"on":[114],"maximum":[116],"temperature.":[117],"benchmark":[119],"circuit":[120],"d695":[121],"been":[123,133],"taken":[124],"difference":[126,140],"temperature":[128,142],"between":[129],"floorplans":[131],"obtained.":[134],"shows":[136],"here":[137],"that":[138],"can":[143],"high":[146],"38K":[148],"modified":[151],"floorplan":[152],"compared":[153],"original":[155],"one.":[156]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
