{"id":"https://openalex.org/W2052862410","doi":"https://doi.org/10.1109/ewdts.2014.7027068","title":"Combinational part structure simplification of fully delay testable sequential circuit","display_name":"Combinational part structure simplification of fully delay testable sequential circuit","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2052862410","doi":"https://doi.org/10.1109/ewdts.2014.7027068","mag":"2052862410"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2014.7027068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2014.7027068","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design &amp; Test Symposium (EWDTS 2014)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059600435","display_name":"A. Matrosova","orcid":"https://orcid.org/0000-0002-8662-4740"},"institutions":[{"id":"https://openalex.org/I196355604","display_name":"National Research Tomsk State University","ror":"https://ror.org/02he2nc27","country_code":"RU","type":"education","lineage":["https://openalex.org/I196355604"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"A. Matrosova","raw_affiliation_strings":["Department of Applied Mathematics and Cybernetics, Tomsk State University, Tomsk, Russia","Department of Applied Mathematics and Cybernetics, Tomsk state university, Russia"],"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Cybernetics, Tomsk State University, Tomsk, Russia","institution_ids":["https://openalex.org/I196355604"]},{"raw_affiliation_string":"Department of Applied Mathematics and Cybernetics, Tomsk state university, Russia","institution_ids":["https://openalex.org/I196355604"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113823672","display_name":"E. Mitrofanov","orcid":null},"institutions":[{"id":"https://openalex.org/I196355604","display_name":"National Research Tomsk State University","ror":"https://ror.org/02he2nc27","country_code":"RU","type":"education","lineage":["https://openalex.org/I196355604"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"E. Mitrofanov","raw_affiliation_strings":["Department of Applied Mathematics and Cybernetics, Tomsk State University, Tomsk, Russia","Department of Applied Mathematics and Cybernetics, Tomsk state university, Russia"],"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Cybernetics, Tomsk State University, Tomsk, Russia","institution_ids":["https://openalex.org/I196355604"]},{"raw_affiliation_string":"Department of Applied Mathematics and Cybernetics, Tomsk state university, Russia","institution_ids":["https://openalex.org/I196355604"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059954059","display_name":"E. Roumjantseva","orcid":null},"institutions":[{"id":"https://openalex.org/I196355604","display_name":"National Research Tomsk State University","ror":"https://ror.org/02he2nc27","country_code":"RU","type":"education","lineage":["https://openalex.org/I196355604"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"E. Roumjantseva","raw_affiliation_strings":["Department of Applied Mathematics and Cybernetics, Tomsk State University, Tomsk, Russia","Department of Applied Mathematics and Cybernetics, Tomsk state university, Russia"],"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Cybernetics, Tomsk State University, Tomsk, Russia","institution_ids":["https://openalex.org/I196355604"]},{"raw_affiliation_string":"Department of Applied Mathematics and Cybernetics, Tomsk state university, Russia","institution_ids":["https://openalex.org/I196355604"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059600435"],"corresponding_institution_ids":["https://openalex.org/I196355604"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11433387,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.8660091161727905},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7681659460067749},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.7216012477874756},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5873609781265259},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5449650287628174},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.542599618434906},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5191135406494141},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46752241253852844},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4541879892349243},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4437463879585266},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.4369582533836365},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4324477016925812},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38861238956451416},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2601880431175232},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.2025378942489624},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1436319351196289},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13885825872421265},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08928433060646057},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06129536032676697}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.8660091161727905},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7681659460067749},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.7216012477874756},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5873609781265259},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5449650287628174},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.542599618434906},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5191135406494141},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46752241253852844},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4541879892349243},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4437463879585266},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.4369582533836365},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4324477016925812},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38861238956451416},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2601880431175232},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.2025378942489624},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1436319351196289},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13885825872421265},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08928433060646057},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06129536032676697},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2014.7027068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2014.7027068","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design &amp; Test Symposium (EWDTS 2014)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1595368737","https://openalex.org/W2005319125","https://openalex.org/W2024632819","https://openalex.org/W2089775145","https://openalex.org/W2090956884","https://openalex.org/W2096785857","https://openalex.org/W2114615162","https://openalex.org/W2153125146"],"related_works":["https://openalex.org/W2358223609","https://openalex.org/W4240239975","https://openalex.org/W2110968362","https://openalex.org/W2371073331","https://openalex.org/W4238178324","https://openalex.org/W2163776294","https://openalex.org/W1679970298","https://openalex.org/W1592424226","https://openalex.org/W2166402441","https://openalex.org/W2090956884"],"abstract_inverted_index":{"The":[0,22],"method":[1,23],"of":[2,12,28,32,45,54,57,60,75],"a":[3,13,29,33,55],"sequential":[4,34,62],"circuit":[5,14],"design":[6],"based":[7,68],"on":[8,69],"using":[9,70],"mixed":[10],"description":[11],"behavior":[15],"has":[16],"been":[17],"developed":[18],"by":[19],"us":[20],"earlier.":[21],"provides":[24],"fully":[25],"delay":[26],"testability":[27],"combinational":[30,58],"part":[31],"circuit.":[35],"It":[36],"is":[37],"oriented":[38],"to":[39],"cut":[40],"down":[41],"the":[42,46,52,61],"path":[43],"lengths":[44],"obtained":[47],"circuits.":[48],"In":[49],"this":[50],"paper":[51],"possibilities":[53],"simplification":[56],"parts":[59],"circuits":[63],"are":[64,67,84],"considered.":[65],"They":[66],"corrected":[71],"Free":[72],"BDDs":[73],"instead":[74],"ROBDDs":[76],"and":[77],"factorizing":[78],"monotonous":[79],"products.":[80],"Some":[81],"experimental":[82],"results":[83],"given.":[85]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
