{"id":"https://openalex.org/W1964635601","doi":"https://doi.org/10.1109/ewdts.2013.6673159","title":"Real-time interconnection network for single-chip many-core computers","display_name":"Real-time interconnection network for single-chip many-core computers","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1964635601","doi":"https://doi.org/10.1109/ewdts.2013.6673159","mag":"1964635601"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2013.6673159","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673159","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design &amp; Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014530657","display_name":"H. Richter","orcid":"https://orcid.org/0000-0003-0205-0784"},"institutions":[{"id":"https://openalex.org/I43980791","display_name":"Clausthal University of Technology","ror":"https://ror.org/04qb8nc58","country_code":"DE","type":"education","lineage":["https://openalex.org/I43980791"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Harald Richter","raw_affiliation_strings":["Clausthal University of Technology, Germany","Clausthal University of Technology Clausthal\u2010Zellerfeld Germany"],"affiliations":[{"raw_affiliation_string":"Clausthal University of Technology, Germany","institution_ids":["https://openalex.org/I43980791"]},{"raw_affiliation_string":"Clausthal University of Technology Clausthal\u2010Zellerfeld Germany","institution_ids":["https://openalex.org/I43980791"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5014530657"],"corresponding_institution_ids":["https://openalex.org/I43980791"],"apc_list":null,"apc_paid":null,"fwci":0.3625,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62254079,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.841208815574646},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7318201065063477},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6908157467842102},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6586208343505859},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6184505820274353},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4647616147994995},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.43910297751426697},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.42803844809532166},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4110841155052185},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.38026192784309387},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3476582169532776},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34030359983444214},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09118890762329102}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.841208815574646},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7318201065063477},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6908157467842102},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6586208343505859},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6184505820274353},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4647616147994995},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.43910297751426697},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.42803844809532166},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4110841155052185},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.38026192784309387},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3476582169532776},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34030359983444214},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09118890762329102},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2013.6673159","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673159","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design &amp; Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W419638019","https://openalex.org/W1519304056","https://openalex.org/W1963638851","https://openalex.org/W2160642395","https://openalex.org/W4238911100","https://openalex.org/W6631078000"],"related_works":["https://openalex.org/W2075067217","https://openalex.org/W4254709952","https://openalex.org/W2026034687","https://openalex.org/W1687060458","https://openalex.org/W2353466952","https://openalex.org/W2117492357","https://openalex.org/W2609535666","https://openalex.org/W4256116802","https://openalex.org/W4235738893","https://openalex.org/W2148325338"],"abstract_inverted_index":{"A":[0],"real-time":[1],"capable":[2],"interconnection":[3],"network":[4,19],"for":[5],"single":[6],"chip":[7,40],"many-core":[8],"computers":[9],"is":[10,13,46],"presented":[11],"that":[12],"superior":[14],"to":[15,58],"the":[16,27,59],"known":[17],"Benes":[18,60],"because":[20,32],"its":[21,64],"routing":[22,45,66],"algorithm":[23],"scales":[24],"linearly":[25],"with":[26],"number":[28],"of":[29],"switches,":[30],"and":[31,42,50],"it":[33],"has":[34],"a":[35],"modular":[36],"setup":[37],"which":[38],"eases":[39],"synthesis":[41],"test.":[43],"Its":[44],"based":[47],"on":[48],"\u201cseparation":[49],"approximation\u201d.":[51],"This":[52],"method":[53],"can":[54],"also":[55],"be":[56],"applied":[57],"network,":[61],"thus":[62],"making":[63],"looping":[65],"obsolete.":[67]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
