{"id":"https://openalex.org/W1967668957","doi":"https://doi.org/10.1109/ewdts.2013.6673149","title":"Extracting complete set of equations to analyze VHDL-AMS descriptions","display_name":"Extracting complete set of equations to analyze VHDL-AMS descriptions","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1967668957","doi":"https://doi.org/10.1109/ewdts.2013.6673149","mag":"1967668957"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2013.6673149","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673149","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design & Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069871386","display_name":"Arezoo Kamran","orcid":"https://orcid.org/0000-0002-6681-5814"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Arezoo Kamran","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran","[Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048957809","display_name":"Vahid Janfaza","orcid":"https://orcid.org/0000-0002-8656-4848"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Vahid Janfaza","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran","[Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran","[Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5069871386"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05035265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl-ams","display_name":"VHDL-AMS","score":0.9343725442886353},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8913257122039795},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7959945201873779},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.791606068611145},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6212653517723083},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6159876585006714},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6008490920066833},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5552703738212585},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.467672199010849},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42308998107910156},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.40849268436431885},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36237072944641113},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2794467806816101},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24182143807411194},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24165800213813782},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.12255668640136719},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10662150382995605},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08247193694114685}],"concepts":[{"id":"https://openalex.org/C2776513426","wikidata":"https://www.wikidata.org/wiki/Q2744740","display_name":"VHDL-AMS","level":4,"score":0.9343725442886353},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8913257122039795},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7959945201873779},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.791606068611145},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6212653517723083},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6159876585006714},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6008490920066833},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5552703738212585},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.467672199010849},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42308998107910156},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40849268436431885},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36237072944641113},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2794467806816101},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24182143807411194},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24165800213813782},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.12255668640136719},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10662150382995605},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08247193694114685}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2013.6673149","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673149","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design & Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1557797132","https://openalex.org/W2096836306","https://openalex.org/W2112679070","https://openalex.org/W2540184019"],"related_works":["https://openalex.org/W1586741485","https://openalex.org/W2070083638","https://openalex.org/W2543386576","https://openalex.org/W1576549604","https://openalex.org/W3021694037","https://openalex.org/W2091509145","https://openalex.org/W2096642685","https://openalex.org/W2357636087","https://openalex.org/W2536306358","https://openalex.org/W2129583176"],"abstract_inverted_index":{"System":[0],"designers":[1],"are":[2],"increasingly":[3],"interested":[4],"in":[5,49,59,85,93],"the":[6,36,42,94,105],"use":[7],"of":[8,33,39,79,82,97,107],"tools":[9],"and":[10,15,77,104],"methods":[11],"letting":[12],"them":[13],"describe":[14],"simulate":[16],"mixed":[17],"signal":[18],"systems.":[19],"A":[20],"pioneer":[21],"description":[22],"language":[23],"for":[24,75],"this":[25,34,62,65],"purpose":[26],"is":[27,47],"VHDL-AMS.":[28],"Due":[29],"to":[30],"special":[31],"features":[32],"language,":[35],"traditional":[37],"method":[38,45],"analog-circuits":[40],"analysis,":[41],"nodal":[43],"analysis":[44,76,95],"that":[46,71],"used":[48,58,74,92],"most":[50],"analog":[51,80],"simulators,":[52],"such":[53],"as":[54],"SPICE,":[55],"cannot":[56],"be":[57,73],"simulators":[60],"using":[61],"language.":[63,87],"In":[64],"paper":[66],"we":[67],"present":[68],"an":[69],"algorithm":[70,89],"can":[72],"simulation":[78],"parts":[81],"systems":[83],"described":[84],"VHDL-AMS":[86],"This":[88],"has":[90,110],"been":[91,111],"engine":[96],"a":[98],"mixed-signal":[99],"simulator":[100],"based":[101],"on":[102],"VHDL-AMS,":[103],"validity":[106],"its":[108],"operation":[109],"shown.":[112]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}