{"id":"https://openalex.org/W2090956884","doi":"https://doi.org/10.1109/ewdts.2013.6673138","title":"Delay testable sequential circuit designs","display_name":"Delay testable sequential circuit designs","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2090956884","doi":"https://doi.org/10.1109/ewdts.2013.6673138","mag":"2090956884"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2013.6673138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design &amp; Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059600435","display_name":"A. Matrosova","orcid":"https://orcid.org/0000-0002-8662-4740"},"institutions":[{"id":"https://openalex.org/I196355604","display_name":"National Research Tomsk State University","ror":"https://ror.org/02he2nc27","country_code":"RU","type":"education","lineage":["https://openalex.org/I196355604"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"A. Matrosova","raw_affiliation_strings":["Tomsk State University","Tomsk State University,, Tomsk,, Russia"],"affiliations":[{"raw_affiliation_string":"Tomsk State University","institution_ids":["https://openalex.org/I196355604"]},{"raw_affiliation_string":"Tomsk State University,, Tomsk,, Russia","institution_ids":["https://openalex.org/I196355604"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113823672","display_name":"E. Mitrofanov","orcid":null},"institutions":[{"id":"https://openalex.org/I196355604","display_name":"National Research Tomsk State University","ror":"https://ror.org/02he2nc27","country_code":"RU","type":"education","lineage":["https://openalex.org/I196355604"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"E. Mitrofanov","raw_affiliation_strings":["Tomsk State University","Tomsk State University,, Tomsk,, Russia"],"affiliations":[{"raw_affiliation_string":"Tomsk State University","institution_ids":["https://openalex.org/I196355604"]},{"raw_affiliation_string":"Tomsk State University,, Tomsk,, Russia","institution_ids":["https://openalex.org/I196355604"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101902034","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0001-6177-9642"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V. Singh","raw_affiliation_strings":["Indian Institute of Technology","Indian Institute of Technology  (India)"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology","institution_ids":[]},{"raw_affiliation_string":"Indian Institute of Technology  (India)","institution_ids":["https://openalex.org/I64295750"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059600435"],"corresponding_institution_ids":["https://openalex.org/I196355604"],"apc_list":null,"apc_paid":null,"fwci":1.2608,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.81064191,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"55","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7994071245193481},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7706526517868042},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.7553262710571289},{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.7465702891349792},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6249994039535522},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.6122175455093384},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6101370453834534},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6004046201705933},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5756844282150269},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5575312376022339},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.5106673836708069},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4334251880645752},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42365872859954834},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4137061536312103},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3988655209541321},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24727317690849304},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.224770188331604},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.22033819556236267},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.15450450778007507},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1486421525478363},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.08505910634994507}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7994071245193481},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7706526517868042},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.7553262710571289},{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.7465702891349792},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6249994039535522},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.6122175455093384},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6101370453834534},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6004046201705933},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5756844282150269},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5575312376022339},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.5106673836708069},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4334251880645752},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42365872859954834},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4137061536312103},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3988655209541321},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24727317690849304},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.224770188331604},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.22033819556236267},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.15450450778007507},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1486421525478363},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.08505910634994507},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2013.6673138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design &amp; Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7200000286102295,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1508825734","https://openalex.org/W1542519739","https://openalex.org/W2024632819","https://openalex.org/W2077157541","https://openalex.org/W2089775145","https://openalex.org/W2096785857","https://openalex.org/W6630622925","https://openalex.org/W6656470888"],"related_works":["https://openalex.org/W2133001125","https://openalex.org/W1936629927","https://openalex.org/W1679970298","https://openalex.org/W1554759374","https://openalex.org/W1592424226","https://openalex.org/W2125277664","https://openalex.org/W2388266617","https://openalex.org/W4240821575","https://openalex.org/W2166402441","https://openalex.org/W2090956884"],"abstract_inverted_index":{"New":[0],"method":[1,42,69],"of":[2,12,22,31,47,51,56,77],"a":[3,23,48,52],"sequential":[4,24,53],"circuit":[5,14,25],"design":[6],"based":[7],"on":[8],"using":[9],"mixed":[10],"description":[11],"the":[13,29,74,78],"behavior":[15,21],"is":[16,26,70],"suggested.":[17,67],"A":[18],"combinational":[19,49],"part":[20,50],"represented":[27],"with":[28],"composition":[30],"ROBDDs":[32],"(Reduced":[33],"Ordered":[34],"Binary":[35],"Decision":[36],"Diagrams)":[37],"and":[38],"monotonous":[39],"products.":[40],"The":[41,68],"provides":[43],"fully":[44],"delay":[45],"testability":[46],"circuit.":[54],"Algorithms":[55],"deriving":[57],"test":[58],"pairs":[59],"for":[60],"robust":[61],"PDFs":[62],"(Path":[63],"Delay":[64],"Faults)":[65],"are":[66],"oriented":[71],"to":[72],"cut":[73],"path":[75],"lengths":[76],"obtained":[79],"circuits.":[80]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
