{"id":"https://openalex.org/W1988679946","doi":"https://doi.org/10.1109/ewdts.2013.6673107","title":"The hardware architecture and device for accurate time signal processing","display_name":"The hardware architecture and device for accurate time signal processing","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1988679946","doi":"https://doi.org/10.1109/ewdts.2013.6673107","mag":"1988679946"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2013.6673107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design &amp; Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5107870597","display_name":"Jiri Dostal","orcid":null},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Jiri Dostal","raw_affiliation_strings":["Czech Technical University, Prague","Fac. of Inf. Technol., Czech Tech. Univ. in Prague, Prague, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Czech Technical University, Prague","institution_ids":["https://openalex.org/I44504214"]},{"raw_affiliation_string":"Fac. of Inf. Technol., Czech Tech. Univ. in Prague, Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079275302","display_name":"Vladim\u00edr Smotlacha","orcid":"https://orcid.org/0000-0001-5961-1453"},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Vladimir Smotlacha","raw_affiliation_strings":["Czech Technical University, Prague","Czech Tech. Univ. in Prague, Prague, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Czech Technical University, Prague","institution_ids":["https://openalex.org/I44504214"]},{"raw_affiliation_string":"Czech Tech. Univ. in Prague, Prague, Czech Republic","institution_ids":["https://openalex.org/I44504214"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5107870597"],"corresponding_institution_ids":["https://openalex.org/I44504214"],"apc_list":null,"apc_paid":null,"fwci":0.7094,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.73386646,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10767","display_name":"Advanced Photonic Communication Systems","score":0.9855999946594238,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8673875331878662},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6946126818656921},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6198423504829407},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5542426109313965},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.5523053407669067},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5336350202560425},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4731225371360779},{"id":"https://openalex.org/keywords/transfer","display_name":"Transfer (computing)","score":0.47149795293807983},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4534462094306946},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.43324440717697144},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.16044515371322632}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8673875331878662},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6946126818656921},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6198423504829407},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5542426109313965},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.5523053407669067},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5336350202560425},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4731225371360779},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.47149795293807983},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4534462094306946},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.43324440717697144},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.16044515371322632},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2013.6673107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design &amp; Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W298756693","https://openalex.org/W1996874179","https://openalex.org/W2163805454","https://openalex.org/W2608876992","https://openalex.org/W6736831959"],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W4210376836","https://openalex.org/W4210925376","https://openalex.org/W4399458808","https://openalex.org/W1633995705","https://openalex.org/W2596211269","https://openalex.org/W2367348190","https://openalex.org/W2014165129","https://openalex.org/W594316872"],"abstract_inverted_index":{"The":[0],"paper":[1],"describes":[2],"architecture,":[3],"design":[4],"and":[5],"implementation":[6],"of":[7,37],"accurate":[8],"time":[9,27],"interval":[10],"counter":[11,42],"into":[12,22],"the":[13,23],"FPGA":[14],"(field-programmable":[15],"gate":[16],"array)":[17],"structure.":[18],"We":[19,32],"embedded":[20],"it":[21],"specialized":[24],"adaptor":[25],"for":[26],"transfer":[28],"over":[29],"optical":[30],"links.":[31],"also":[33],"present":[34],"achieved":[35],"results":[36],"comparison":[38],"with":[39],"precise":[40],"commercial":[41],"SR-620.":[43]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
