{"id":"https://openalex.org/W2032893376","doi":"https://doi.org/10.1109/ewdts.2013.6673084","title":"Hybrid history-based test overlapping to reduce test application time","display_name":"Hybrid history-based test overlapping to reduce test application time","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2032893376","doi":"https://doi.org/10.1109/ewdts.2013.6673084","mag":"2032893376"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2013.6673084","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673084","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design & Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048957809","display_name":"Vahid Janfaza","orcid":"https://orcid.org/0000-0002-8656-4848"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Vahid Janfaza","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108389380","display_name":"Bahjat Forouzandeh","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Bahjat Forouzandeh","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032487759","display_name":"Payman Behnam","orcid":"https://orcid.org/0000-0002-3826-9123"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Payman Behnam","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012903661","display_name":"M. Hassan Najafi","orcid":"https://orcid.org/0000-0002-4655-6229"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohammadreza Najafi","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5048957809"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.09972324,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8944331407546997},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7481805682182312},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.715506911277771},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6713190674781799},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.6528691053390503},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.544069766998291},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.45575541257858276},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45491743087768555},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4478960633277893},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4218064844608307},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.360128790140152},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3506969213485718},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34455370903015137},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3404691219329834},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3211557865142822},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.31799185276031494},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16558322310447693},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07494097948074341}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8944331407546997},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7481805682182312},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.715506911277771},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6713190674781799},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.6528691053390503},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.544069766998291},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.45575541257858276},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45491743087768555},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4478960633277893},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4218064844608307},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.360128790140152},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3506969213485718},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34455370903015137},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3404691219329834},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3211557865142822},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.31799185276031494},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16558322310447693},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07494097948074341},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2013.6673084","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673084","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design & Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W646410877","https://openalex.org/W1554885925","https://openalex.org/W1899662483","https://openalex.org/W2010806198","https://openalex.org/W2058549720","https://openalex.org/W2116315480","https://openalex.org/W2156546262","https://openalex.org/W2163814338","https://openalex.org/W2504986731","https://openalex.org/W2553126414","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W2789883751","https://openalex.org/W2143881398","https://openalex.org/W2147986372","https://openalex.org/W1979305473","https://openalex.org/W2274367941","https://openalex.org/W2075356617","https://openalex.org/W2074302528","https://openalex.org/W2092894550","https://openalex.org/W3088373974","https://openalex.org/W2105463797"],"abstract_inverted_index":{"In":[0,41],"spite":[1],"of":[2],"significant":[3],"efforts":[4],"in":[5,57,81],"circuit":[6,9],"testing,":[7],"sequential":[8,59],"testing":[10],"has":[11],"remained":[12],"a":[13,44],"challenging":[14],"problem.":[15],"Existing":[16],"test":[17,48,55,79],"solutions":[18],"like":[19],"scan":[20],"methods":[21,33],"are":[22],"proposed":[23],"to":[24,53,69],"facilitate":[25],"Automatic":[26],"Test":[27],"Pattern":[28],"Generation":[29],"(ATPG),":[30],"however,":[31],"these":[32],"suffer":[34],"from":[35],"large":[36],"area":[37],"and":[38],"delay":[39],"overhead.":[40],"this":[42],"paper,":[43],"new":[45],"hybrid":[46],"history-based":[47],"overlapping":[49],"method":[50],"is":[51,67],"presented":[52],"reduce":[54],"time":[56,80],"scan-based":[58],"circuits":[60],"while":[61],"almost":[62],"no":[63],"extra":[64],"hardware":[65],"overhead":[66],"imposed":[68],"the":[70],"circuit.":[71],"Experimental":[72],"results":[73],"show":[74],"30%":[75],"reduction":[76],"on":[77],"average":[78],"comparison":[82],"with":[83],"existing":[84],"works.":[85]},"counts_by_year":[{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}