{"id":"https://openalex.org/W2144478983","doi":"https://doi.org/10.1109/ewdts.2010.5742108","title":"Algebra-logical repair method for FPGA logic blocks","display_name":"Algebra-logical repair method for FPGA logic blocks","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2144478983","doi":"https://doi.org/10.1109/ewdts.2010.5742108","mag":"2144478983"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2010.5742108","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2010.5742108","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044434351","display_name":"Vladimir Hahanov","orcid":"https://orcid.org/0000-0001-5312-5841"},"institutions":[{"id":"https://openalex.org/I107158390","display_name":"Kharkiv National University of Radio Electronics","ror":"https://ror.org/01ctj1b90","country_code":"UA","type":"education","lineage":["https://openalex.org/I107158390"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"Vladimir Hahanov","raw_affiliation_strings":["Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","institution_ids":["https://openalex.org/I107158390"]},{"raw_affiliation_string":"Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine","institution_ids":["https://openalex.org/I107158390"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039700835","display_name":"Sergey Galagan","orcid":null},"institutions":[{"id":"https://openalex.org/I107158390","display_name":"Kharkiv National University of Radio Electronics","ror":"https://ror.org/01ctj1b90","country_code":"UA","type":"education","lineage":["https://openalex.org/I107158390"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"Sergey Galagan","raw_affiliation_strings":["Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","institution_ids":["https://openalex.org/I107158390"]},{"raw_affiliation_string":"Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine","institution_ids":["https://openalex.org/I107158390"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075913416","display_name":"Vitaliy Olchovoy","orcid":null},"institutions":[{"id":"https://openalex.org/I107158390","display_name":"Kharkiv National University of Radio Electronics","ror":"https://ror.org/01ctj1b90","country_code":"UA","type":"education","lineage":["https://openalex.org/I107158390"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"Vitaliy Olchovoy","raw_affiliation_strings":["Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","institution_ids":["https://openalex.org/I107158390"]},{"raw_affiliation_string":"Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine","institution_ids":["https://openalex.org/I107158390"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026812720","display_name":"Aleksey Priymak","orcid":null},"institutions":[{"id":"https://openalex.org/I107158390","display_name":"Kharkiv National University of Radio Electronics","ror":"https://ror.org/01ctj1b90","country_code":"UA","type":"education","lineage":["https://openalex.org/I107158390"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"Aleksey Priymak","raw_affiliation_strings":["Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty, Kharkiv National University of Radioelectronics, Kharkiv, Ukraine","institution_ids":["https://openalex.org/I107158390"]},{"raw_affiliation_string":"Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine","institution_ids":["https://openalex.org/I107158390"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.17518587,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"7","issue":null,"first_page":"482","last_page":"487"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8434967994689941},{"id":"https://openalex.org/keywords/operability","display_name":"Operability","score":0.7562878131866455},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6959972381591797},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.491328626871109},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4624370038509369},{"id":"https://openalex.org/keywords/boolean-algebra","display_name":"Boolean algebra","score":0.4603211283683777},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4398610591888428},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42747583985328674},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.36680787801742554},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3462498188018799},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23507753014564514}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8434967994689941},{"id":"https://openalex.org/C126231374","wikidata":"https://www.wikidata.org/wiki/Q1061298","display_name":"Operability","level":2,"score":0.7562878131866455},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6959972381591797},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.491328626871109},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4624370038509369},{"id":"https://openalex.org/C39685927","wikidata":"https://www.wikidata.org/wiki/Q173183","display_name":"Boolean algebra","level":2,"score":0.4603211283683777},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4398610591888428},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42747583985328674},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36680787801742554},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3462498188018799},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23507753014564514},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2010.5742108","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2010.5742108","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W89984018","https://openalex.org/W1996166609","https://openalex.org/W2019738331","https://openalex.org/W2096794779","https://openalex.org/W2104057784","https://openalex.org/W2105120486","https://openalex.org/W2107577926","https://openalex.org/W2112375479","https://openalex.org/W2120291720","https://openalex.org/W2139258857","https://openalex.org/W2147178958","https://openalex.org/W2147289806","https://openalex.org/W2153215716","https://openalex.org/W2153497163","https://openalex.org/W2157843090","https://openalex.org/W2166521894","https://openalex.org/W2169342007","https://openalex.org/W2170989167","https://openalex.org/W2400908863","https://openalex.org/W6603589353","https://openalex.org/W6682097915"],"related_works":["https://openalex.org/W2147419146","https://openalex.org/W2135636985","https://openalex.org/W2197466303","https://openalex.org/W1607849496","https://openalex.org/W2462231960","https://openalex.org/W2139569078","https://openalex.org/W2136570321","https://openalex.org/W2368888192","https://openalex.org/W1512285683","https://openalex.org/W4252227487"],"abstract_inverted_index":{"An":[0],"algebra-logical":[1],"repair":[2,66],"method":[3,33],"for":[4,27,36],"FPGA":[5,41,68],"functional":[6],"logic":[7,69],"blocks":[8,42],"on":[9,22],"the":[10,14,38,59,67],"basis":[11],"of":[12,40,62],"solving":[13],"coverage":[15],"problem":[16],"is":[17,20,34],"proposed.":[18],"It":[19,49],"focused":[21],"implementation":[23],"into":[24],"Infrastructure":[25],"IP":[26],"system-on-a":[28],"chip":[29],"and":[30,43,54],"system-in-package.":[31],"A":[32],"designed":[35],"providing":[37],"operability":[39],"digital":[44],"system":[45],"as":[46],"a":[47],"whole.":[48],"enables":[50],"to":[51,65],"obtain":[52],"exact":[53],"optimal":[55],"solution":[56],"associated":[57],"with":[58,71],"minimum":[60],"number":[61],"spares":[63],"needed":[64],"components":[70],"multiple":[72],"faults.":[73]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}