{"id":"https://openalex.org/W2098595470","doi":"https://doi.org/10.1109/ewdts.2010.5742035","title":"Facilitating testability of TLM FIFO: SystemC implementations","display_name":"Facilitating testability of TLM FIFO: SystemC implementations","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2098595470","doi":"https://doi.org/10.1109/ewdts.2010.5742035","mag":"2098595470"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2010.5742035","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2010.5742035","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055237181","display_name":"Homa Alemzadeh","orcid":"https://orcid.org/0000-0001-5279-842X"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Homa Alemzadeh","raw_affiliation_strings":["CAD Research Group, ECE Department, University of Tehran, Tehran, Iran","CAD Research Group, ECE Department, University of Tehran, 14399, Iran"],"affiliations":[{"raw_affiliation_string":"CAD Research Group, ECE Department, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"CAD Research Group, ECE Department, University of Tehran, 14399, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038900774","display_name":"Marco Cimei","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Cimei","raw_affiliation_strings":["Dipartimento di Automatic e Informatica, Politecnico di Turino, Torino, Italy","Dipartimento di Automatica e Informatica, Politecnico di Torino, I-10129, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatic e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, I-10129, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036258272","display_name":"P. Prinetto","orcid":"https://orcid.org/0000-0003-2400-8245"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Paolo Prinetto","raw_affiliation_strings":["Dipartimento di Automatic e Informatica, Politecnico di Turino, Torino, Italy","Dipartimento di Automatica e Informatica, Politecnico di Torino, I-10129, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatic e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, I-10129, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["CAD Research Group, ECE Department, University of Tehran, Tehran, Iran","CAD Research Group, ECE Department, University of Tehran, 14399, Iran"],"affiliations":[{"raw_affiliation_string":"CAD Research Group, ECE Department, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"CAD Research Group, ECE Department, University of Tehran, 14399, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5055237181"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15158524,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"428","last_page":"431"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9637892246246338},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.894455075263977},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8278698921203613},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.8224529027938843},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6973523497581482},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6648997068405151},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5673701763153076},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5343049764633179},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4938841462135315},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4841407239437103},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.42220309376716614},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38567131757736206},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3400191366672516},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2696898579597473},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1549868881702423}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9637892246246338},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.894455075263977},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8278698921203613},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.8224529027938843},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6973523497581482},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6648997068405151},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5673701763153076},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5343049764633179},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4938841462135315},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4841407239437103},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.42220309376716614},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38567131757736206},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3400191366672516},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2696898579597473},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1549868881702423},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2010.5742035","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2010.5742035","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 East-West Design & Test Symposium (EWDTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2099095915","https://openalex.org/W2127143495","https://openalex.org/W2148740615","https://openalex.org/W6682087946"],"related_works":["https://openalex.org/W2098595470","https://openalex.org/W1525398417","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W2266880325","https://openalex.org/W2097331811","https://openalex.org/W2112120387","https://openalex.org/W1981924702","https://openalex.org/W2532163536","https://openalex.org/W2157772069"],"abstract_inverted_index":{"TLM":[0,60,65],"is":[1],"a":[2,18],"high-level":[3,56],"approach":[4],"to":[5,26,80],"modeling":[6],"digital":[7],"systems":[8],"with":[9],"an":[10],"emphasis":[11],"on":[12,50],"separating":[13],"computations":[14],"from":[15],"communications":[16],"within":[17],"system.":[19],"With":[20],"the":[21,29,51,63,81,91,98],"evolution":[22],"of":[23,33,44,53,90,100],"design":[24],"methodologies":[25],"transaction":[27],"level":[28,43],"need":[30],"for":[31,36,59],"definition":[32],"DFT":[34],"(Design":[35],"Test)":[37],"techniques":[38],"at":[39],"this":[40],"very":[41],"high":[42],"abstraction":[45],"arises.":[46],"This":[47],"paper":[48],"focuses":[49],"implementation":[52],"three":[54],"different":[55],"testing":[57],"strategies":[58,69],"FIFO":[61],"as":[62],"basic":[64],"communication":[66],"channel.":[67],"These":[68],"are":[70],"implemented":[71],"by":[72],"adding":[73],"Built-in":[74],"Functional":[75],"Self":[76],"Test":[77],"(BIFST)":[78],"utilities":[79,92],"channels":[82],"and":[83,104],"computation":[84],"units.":[85],"We":[86],"present":[87],"SystemC":[88,102],"implementations":[89],"that":[93],"we":[94],"have":[95],"developed":[96],"in":[97],"form":[99],"new":[101],"classes":[103],"methods.":[105]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}