{"id":"https://openalex.org/W2138208643","doi":"https://doi.org/10.1109/ewdts.2008.5580152","title":"A novel timing-driven placement algorithm using smooth timing analysis","display_name":"A novel timing-driven placement algorithm using smooth timing analysis","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2138208643","doi":"https://doi.org/10.1109/ewdts.2008.5580152","mag":"2138208643"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2008.5580152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2008.5580152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030508367","display_name":"Andrey Ayupov","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrey Ayupov","raw_affiliation_strings":["Strategic CAD Labs, Intel Corp","Strategic Cad Labs, Intel Corporation, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corp","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic Cad Labs, Intel Corporation, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046216435","display_name":"Leonid Kraginskiy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Leonid Kraginskiy","raw_affiliation_strings":["Strategic CAD Labs, Intel Corp","Strategic Cad Labs, Intel Corporation, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corp","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic Cad Labs, Intel Corporation, , USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.15413455,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"137","last_page":"140"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.8261053562164307},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7069293260574341},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5779094696044922},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5581414103507996},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5571258664131165},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5355939865112305},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.5009562969207764},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4883281886577606},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.4764321744441986},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.45328289270401},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.4406175911426544},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.4118381142616272},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.35186439752578735},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.23599499464035034},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.17458432912826538},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15414643287658691},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.11811530590057373},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09909164905548096}],"concepts":[{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.8261053562164307},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7069293260574341},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5779094696044922},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5581414103507996},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5571258664131165},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5355939865112305},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.5009562969207764},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4883281886577606},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.4764321744441986},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.45328289270401},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.4406175911426544},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.4118381142616272},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.35186439752578735},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.23599499464035034},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.17458432912826538},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15414643287658691},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.11811530590057373},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09909164905548096},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2008.5580152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2008.5580152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W107761332","https://openalex.org/W1990112502","https://openalex.org/W2070072634","https://openalex.org/W2114871550","https://openalex.org/W2171141198"],"related_works":["https://openalex.org/W2145535176","https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W1804063983","https://openalex.org/W1570180536","https://openalex.org/W2134944363","https://openalex.org/W2087387686","https://openalex.org/W3140640533","https://openalex.org/W2129468521","https://openalex.org/W1516835811"],"abstract_inverted_index":{"This":[0],"work":[1],"proposes":[2],"a":[3,9,28,42,59,91,101],"timing-driven":[4,73],"placement":[5,53,74],"algorithm":[6,40],"that":[7,46,65],"uses":[8,41],"new":[10],"type":[11],"of":[12,31],"timing":[13,19,24],"analysis,":[14],"which":[15],"we":[16],"call":[17],"smooth":[18,29],"analysis.":[20],"It":[21],"constructs":[22],"the":[23,39,66],"cost":[25],"function":[26,30],"as":[27,58],"cell":[32],"placement.":[33],"In":[34],"addition,":[35],"for":[36,76],"net":[37,44],"modeling":[38],"companion":[43],"routing":[45],"provides":[47],"more":[48],"accurate":[49],"wire":[50],"delay.":[51],"The":[52],"task":[54],"is":[55,69],"then":[56],"formulated":[57],"non-linear":[60],"optimization":[61],"problem.":[62],"Experiments":[63],"prove":[64],"proposed":[67],"method":[68],"applicable":[70],"to":[71,100],"build":[72],"solutions":[75],"designs":[77,89],"with":[78],"thousands":[79],"critical":[80],"cells.":[81],"Experimental":[82],"results":[83],"on":[84],"blocks":[85],"from":[86],"recent":[87],"microprocessor":[88],"show":[90],"65%":[92],"average":[93],"improvement":[94],"in":[95],"total":[96],"negative":[97],"slack":[98],"comparing":[99],"leading":[102],"industrial":[103],"flow.":[104]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}