{"id":"https://openalex.org/W2129710216","doi":"https://doi.org/10.1109/ewdts.2008.5580143","title":"Utilizing HDL simulation engines for accelerating design and test processes","display_name":"Utilizing HDL simulation engines for accelerating design and test processes","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2129710216","doi":"https://doi.org/10.1109/ewdts.2008.5580143","mag":"2129710216"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2008.5580143","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2008.5580143","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027321193","display_name":"Najmeh Farajipour Ghohroud","orcid":"https://orcid.org/0000-0002-0699-5059"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Najmeh Farajipour","raw_affiliation_strings":["Faculty of Engineering, University of Tehran, Tehran, IRAN","CAD Res. Group, Univ. of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, University of Tehran, Tehran, IRAN","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"CAD Res. Group, Univ. of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079879975","display_name":"S. Behdad Hosseini","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"S. Behdad Hosseini","raw_affiliation_strings":["Faculty of Engineering, University of Tehran, Tehran, IRAN","CAD Res. Group, Univ. of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, University of Tehran, Tehran, IRAN","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"CAD Res. Group, Univ. of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["Faculty of Engineering, University of Tehran, Tehran, IRAN","CAD Res. Group, Univ. of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, University of Tehran, Tehran, IRAN","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"CAD Res. Group, Univ. of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7266,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.86658608,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"371","last_page":"375"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7301478385925293},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6870052814483643},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6451972126960754},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5639348030090332},{"id":"https://openalex.org/keywords/vhdl-ams","display_name":"VHDL-AMS","score":0.5525484085083008},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5267055630683899},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.49892497062683105},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4485085904598236},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.43081557750701904},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4259951114654541},{"id":"https://openalex.org/keywords/fault-simulator","display_name":"Fault Simulator","score":0.42250046133995056},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4210275113582611},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3866517245769501},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35646942257881165},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3423765301704407},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3204748034477234},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3151906728744507},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.2519192099571228},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.2087203860282898},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19637292623519897},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.1802094578742981},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1726984977722168},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15097996592521667},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14350390434265137},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09250801801681519}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7301478385925293},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6870052814483643},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6451972126960754},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5639348030090332},{"id":"https://openalex.org/C2776513426","wikidata":"https://www.wikidata.org/wiki/Q2744740","display_name":"VHDL-AMS","level":4,"score":0.5525484085083008},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5267055630683899},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.49892497062683105},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4485085904598236},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.43081557750701904},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4259951114654541},{"id":"https://openalex.org/C2776365744","wikidata":"https://www.wikidata.org/wiki/Q5438149","display_name":"Fault Simulator","level":5,"score":0.42250046133995056},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4210275113582611},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3866517245769501},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35646942257881165},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3423765301704407},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3204748034477234},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3151906728744507},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.2519192099571228},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.2087203860282898},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19637292623519897},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.1802094578742981},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1726984977722168},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15097996592521667},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14350390434265137},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09250801801681519},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2008.5580143","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2008.5580143","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W632146583","https://openalex.org/W1578014232","https://openalex.org/W1583437159","https://openalex.org/W2061011207","https://openalex.org/W2076000316","https://openalex.org/W2138993691","https://openalex.org/W2157006704","https://openalex.org/W2170851517","https://openalex.org/W2171562970","https://openalex.org/W4210836009","https://openalex.org/W6634570242","https://openalex.org/W6685295446"],"related_works":["https://openalex.org/W1586741485","https://openalex.org/W2112319484","https://openalex.org/W1967668957","https://openalex.org/W2086925677","https://openalex.org/W2540912367","https://openalex.org/W4236466949","https://openalex.org/W2151941088","https://openalex.org/W2357636087","https://openalex.org/W2115181119","https://openalex.org/W2103595924"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,21,46],"complete":[4],"test":[5,18,30,59],"package":[6],"in":[7,45,58],"VHDL":[8,57],"that":[9],"makes":[10],"it":[11],"possible":[12],"to":[13,39],"simulate":[14],"faults":[15],"and":[16,35,42,49,69],"generate":[17],"patterns":[19],"for":[20,66],"component":[22],"during":[23],"its":[24],"design":[25],"process.":[26],"Different":[27],"approaches":[28,65],"on":[29],"applications":[31],"can":[32],"be":[33,37],"combined":[34],"then":[36],"applied":[38],"combinational,":[40],"sequential":[41],"scan-based":[43],"circuits":[44],"fully":[47],"configurable":[48],"convenient":[50],"environment.":[51],"To":[52],"reveal":[53],"the":[54],"capabilities":[55],"of":[56],"configurations,":[60],"we":[61],"used":[62],"two":[63],"different":[64],"fault":[67],"simulation":[68],"evaluated":[70],"them":[71],"with":[72],"random":[73],"tests.":[74]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}